Hi,Originally posted in cdnusers.org by Jack
I work for a university and I am fairly new to Cadence. Currently we are working on a project that requires designing digital IC using custom cell libraries. In other words, we will not be using regular Boolean gates like AND, OR, or XOR. The tentative design flow is as follows:
1. Design the transistor-level schematic and layout for each custom logic gate in Cadence;
2. Design structural VHDL/Verilog code using these custom logic gates as components and specify the connectivity;
3. "Synthesize" or "Import" the HDL code into Cadence to automatically create schematic based on the transistor-level schematic of the custom logic gates;
4. Simulate the design in Cadence;
5. Automatically generate the layout.
Well, I am not sure whether this flow is practical or not. But if there are appropriate tools to do these, it'll be extremely helpful. Please let me know what tools we should use to perform these steps. Thanks. I really appreciate it.