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 PLE adjusting in Rtl compiler 

Last post Fri, Oct 27 2006 2:32 PM by archive. 13 replies.
Started by archive 27 Oct 2006 02:32 PM. Topic has 13 replies and 3081 views
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  • Fri, Oct 27 2006 2:32 PM

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    PLE adjusting in Rtl compiler Reply

    Hi guys,

    Does anybody know how to adjust PLE setting in RTL compiler so it will be more in line with encounter results?

    I heard somebody talk about it, but he is not available now.

    Any help would be appreciated.

    Thanks,

    Manzur.


    Originally posted in cdnusers.org by myazdani
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  • Wed, Nov 1 2006 10:06 PM

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    RE: PLE adjusting in Rtl compiler Reply

    Hi,

    I am not sure what you are looking for exactly but here are a few things I can think about.

    • Adjusting aspect ratio:
      • set_attribute aspect_ratio /
      • or read_def
    • Controlling the number of metal layer used
      • set_attribute number_of_routing_layers
    Also make sure you are pointing to the same cap_table and lef files as the one FE is using.

    Eric.


    Originally posted in cdnusers.org by evenditti
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  • Thu, Nov 2 2006 2:07 PM

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    RE: PLE adjusting in Rtl compiler Reply

    Hi,

    In addition to the above attributes, set the scale factors to the same ones used in SOC-Encounter. Two scale factors are used to align SOC-E trial route/default extraction with final route and sign off extraction. These R and C scale factors should be set to the same value in RC.

    set_attr scale_of_cap_per_unit_len
    set_attr scale_of_res_per_unit_len

    Remember that there will be differences between the PLE and FE results. The goal of PLE is to give a better starting point for place and route.

    Thanks,
    Rich


    Originally posted in cdnusers.org by richo
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  • Fri, Nov 3 2006 8:01 PM

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    RE: PLE adjusting in Rtl compiler Reply

    Thanks for your help. I am going to be using the scaling factors for PLE tuning.

    This forum is great!


    Originally posted in cdnusers.org by myazdani
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  • Wed, Jan 31 2007 5:12 AM

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    RE: PLE adjusting in Rtl compiler Reply

    I did not found any explanation about how RC computes net lenght in PLE mode. Therefore I am not sure if it is better use PLE thanĀ  wire load models to drive synthesis, can anyone help me?

    Regards,
    Cristiano.


    Originally posted in cdnusers.org by clsantos
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  • Wed, Jan 31 2007 6:43 AM

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    RE: PLE adjusting in Rtl compiler Reply

    Cristiano,
    You will not find any explanation of how RC computes the net length as it is a proprietary algorithm. About all I can tell you is that PLE uses a combination of the information in the LEF and capTable along with the structure of the logic to model the nets more accurately than any wireload. You will find that the results after Place and Route will be better using PLE's. It is important to note that the PLE flow is meant to make the post P&R (read REAL) results better. Depending on how conservative your WLM's are, the QoR results post synthesis could be either better OR worse.

    Hope this helps.

    Regards,

    -Jeff-


    Originally posted in cdnusers.org by jflieder
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  • Wed, Jan 31 2007 7:55 AM

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    RE: PLE adjusting in Rtl compiler Reply

    Hi Cristiano,

    I tried to find out myself but, as you may have found out, R&D keeps this recipie pretty tight to their belt - understandably so. The information I was provided is pretty similar to what jflieder mentioned. The is no doubt in my mind that using some of the physical information available early on is the right approach. In addition to jflieder's comment I would like to point out the following:
    + PLEs are dynamic so every time RC picks a different architecture the consequences on net topology are recomputed
    This is a key difference with WLM which is static in nature
    + I have seen no noticeable impact on runtime or memory usage
    + PLEs can be more localized since they are not bound by hierarchy and fanout only as I understand this
    + In my experience it is a single iteration approach as opposed to constantly tweaking CWLMs over iterations
    + On the designs I have run, PLEs have produce better or comparable results
    One issue I have run into is that it has required a little more dilligence at reviewing all the collateral since now I do not only have to review the .libs but also the physical files. Probably not such a bad thing since we have to review them at some point and better earlier than later.

    good luck,
    GH-


    Originally posted in cdnusers.org by grasshopper
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  • Mon, Jul 9 2007 8:43 AM

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    RE: PLE adjusting in Rtl compiler Reply

    Hello,

    1) How to correlate the timing results between RTL Compiler and pre-layout STA (using ETS or FE-CTE) since it is not possible to reproduce PLE wire prediction ?

    2) What is the recommended way to generate SDF file for pre-layout verification (functional simulation) if write_sdf is an unsupported command in RTL_Compiler?

    Thanks in advance,
    Cristiano.


    Originally posted in cdnusers.org by clsantos
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  • Wed, Jul 11 2007 11:59 AM

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    RE: PLE adjusting in Rtl compiler Reply

    Hi Cristiano,

    how are PLEs treating you these days ? I just downloaded RC71 only to be pleasantly surpsied with fully supported write_sdf. Sounds like you will be as exicted as me :)

    GH-


    Originally posted in cdnusers.org by grasshopper
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  • Thu, Jul 12 2007 12:44 PM

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    RE: PLE adjusting in Rtl compiler Reply

    GH, it is really great!

    Besides that, below is what Cadence support says about correlating PLE results during STA.

    Cristiano.

    #####
    Cristiano.
    RC has the 'write_set_load' command. This command will write out a file
    which includes a set_load for every net in the design. The user can then load
    the netlist and SDCs into the timing tool, followed by this set_load file.
    This *should* enable the timing tool to 'see' the same timing as RC PLE. That
    is, it uses the same wire delays as RC in PLE mode. RC will not tell how PLE
    does it, but it provides the value that PLE picked.
    #####


    Originally posted in cdnusers.org by clsantos
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  • Mon, Aug 6 2007 12:42 PM

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    RE: PLE adjusting in Rtl compiler Reply

    Hello all,

    Unfortunately set_load does not work on nets in CTE (SOCE62).

    I found the following help messages in sourceLink but they are conflicting:
    http://sourcelink.cadence.com/docs/db/kdb/2007/June/11350058.html
    http://sourcelink.cadence.com/docs/db/kdb/2006/June/11249762.html

    So, what is the recommended way to correlate PLE results with STA using CTE?

    Regards,
    Cristiano.


    Originally posted in cdnusers.org by clsantos
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  • Mon, Aug 6 2007 1:16 PM

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    RE: PLE adjusting in Rtl compiler Reply


    Hi Cristiano,

    I believe I ran into this and ETS6.2-USR1 did support set_load on nets. I have not tried it in SOC so I do not know what version of SOC would incorporate the enhancements to CTE and SOC.

    gh-


    Originally posted in cdnusers.org by grasshopper
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  • Mon, Aug 6 2007 1:31 PM

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    RE: PLE adjusting in Rtl compiler Reply

    Hi Cristiano,

    write_spef is also supported in RC 7.1. write_sdf/write_spef/write_set_load are commands available in RC to help correlate PLE results with CTE. I haven't done experiments on which method works best.

    write_ets is also available to provide a starter script to run ETS.

    ETS 6.2 USR1 accepts set_load on nets.

    -NC


    Originally posted in cdnusers.org by nandini
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  • Mon, Aug 6 2007 2:43 PM

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    RE: PLE adjusting in Rtl compiler Reply

    I think set_load will be supported in SOC62USR2 (planned to 08/08/2007).

    I tried the command spefIn using the spef file generated by RC7.1 and it seems be ok.

    Thanks a lot,
    Cristiano.


    Originally posted in cdnusers.org by clsantos
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Started by archive at 27 Oct 2006 02:32 PM. Topic has 13 replies.