Home > Community > Forums > Logic Design > reading synthesized design

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 reading synthesized design 

Last post Fri, Oct 6 2006 12:22 AM by archive. 3 replies.
Started by archive 06 Oct 2006 12:22 AM. Topic has 3 replies and 1142 views
Page 1 of 1 (4 items)
Sort Posts:
  • Fri, Oct 6 2006 12:22 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,950
    reading synthesized design Reply

    Is it possible to read in a synthesized design in rtlcompiler for reporting purposes? I know that in synopsys there is a possibility to read in the .db file and thus not having to re synthesize an old design for reporting purposes. My synthesis takes several hours and one little ctrl z by mistake can end the whole session which can be really frustrating...

    /Mike


    Originally posted in cdnusers.org by mike.c
    • Post Points: 0
  • Fri, Oct 6 2006 2:59 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,950
    RE: reading synthesized design Reply

    you should be able to do the following

    ...
    ...
    after you load your libraries
    ..
    ...
    read_hdl your_last_verilog
    read_sdc your_sdc_file
    elaborate
    report timing


    li siang


    Originally posted in cdnusers.org by lisiang
    • Post Points: 0
  • Tue, Oct 10 2006 8:19 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,950
    RE: reading synthesized design Reply

    Hi Mike,

    Li Siang is right, you can easily reload any verilog netlist and write reports. The only one I've seen that doesn't work for this is reporting on power. I've seen that RC doesn't (always) identify the clock-gating correctly, especially if your original setup files set things like the default activity. Timing, Area, Gates and even DFT work fine.

    Hope this helps,

    CD


    Originally posted in cdnusers.org by crispy_duck
    • Post Points: 0
  • Thu, Oct 12 2006 12:02 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,950
    RE: reading synthesized design Reply

    I never managed to read in the .sdc file properly, instead I use my .tcl constraint files and then It works to some extend. When comparing my old report files with the new ones most of the paths are the same but some differ, is this correct or should the report files come out identical?

    /Mike


    Originally posted in cdnusers.org by mike.c
    • Post Points: 0
Page 1 of 1 (4 items)
Sort Posts:
Started by archive at 06 Oct 2006 12:22 AM. Topic has 3 replies.