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 RC compiler issue with vlog2001 

Last post Mon, Oct 2 2006 4:38 PM by archive. 1 replies.
Started by archive 02 Oct 2006 04:38 PM. Topic has 1 replies and 1042 views
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  • Mon, Oct 2 2006 4:38 PM

    • archive
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    RC compiler issue with vlog2001 Reply

    Hi
    A verilog source file has the following code for inferring a flop with asynchronous reset on posedge
    always @ (posedge clk or posedge rst)
      q[SIZE-1:0]  <= rst ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0]  : din[SIZE-1:0] );
     
    The above is valid vlog2001 syntax. Unfortunately the RTL compiler is erroring out with the following message.

    Error   : An 'if' statement is required at the top of an always block to infer a latch or flip-flop. [VLOGPT-46] [_read_hdl]
            : in file 'swrvr_clib.v' on line 419, column 3.
            : The supported syntax for asynchronous set-reset on a flop-flop is:
        reg data_out;
        always @(posedge clock or posedge reset)
            if ( reset )
                data_out = 1'b1;
            else
                data_out = 1'b0.

    Does RTLC not infer flops in case of vlog2001? Changing the source code is not an option.
    I was wondering if a user-option had been left out in the config file.

    Appreciate any help in this matter
    -Sudeep


    Originally posted in cdnusers.org by sudeep_ghosh
    • Post Points: 0
  • Tue, Oct 3 2006 7:51 AM

    • archive
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    RE: RC compiler issue with vlog2001 Reply

    Hi Sudeep,
    That style of coding for flip-flop is not supported for synthesis. Please view the HDL Modelling Guider here: http://sourcelink.cadence.com/docs/files/Release_Info/Docs/rc_hdlmod/rc_hdlmod6.1.2/rc_hdlmodTOC.html


    Originally posted in cdnusers.org by synthman
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Started by archive at 02 Oct 2006 04:38 PM. Topic has 1 replies.