thanks to ajeetha. The information given by nchelp for mnemonic SDFNMX:
SDF annotation is not permitted on any segment (both digital & analog) of mixed-signal.
The annotated delay will be ignored, and circuit will be simulated without delay.
This explains the second problem, I was having. Every INTERCONNECT timing arc, that is interfacing with the makro (to be synthesized as a verilog-ams-netlist), throws that warning. The ignorance of the analog nets is ok, their delays are negligible small anyway. But I would really like ncsim to respect the sdf-annotation on some digital nets. The problem goes that far, that all INTERCONNECTS on the pathes from the input-pins to the makro are ignored.
But I did not find a way to declare a net as digital in a transistor-level-verilogams-netlist nor to tell ncelab to strictly honor these interconnects. I don't suppose, there is a way?
(If I declare the signal digital in the testbench, ncism will not run, because it doesn't know how to interpret this signal at the makro.)
The lines given by the warning-message are the ones in the verilog-simulation-file. So, I can't be sure, which ones in the SDF are ignored. But since I changed the simulation files for sdf3.0-compliance because of sdf-warnings, that the timing arcs to be annotated cannot be found (in some sequential cells), I think, these warnings refer to INTERCONNECT arcs.
Oh, guys, I am sorry for the fuss, I just found out, what caused the warnings with the sequential cells: I still had the generated clock in the testbench (from an earlier version of the block under test), described as an analog signal. That's all.
That only leaves me with the real mixed-signal problem. *g*
Thanks for your help.
Bye, PNR.Originally posted in cdnusers.org by PNR