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 starting RTL compiler and Encounter 

Last post Wed, Nov 9 2011 1:22 PM by grasshopper. 1 replies.
Started by jun1119 03 Nov 2011 11:25 AM. Topic has 1 replies and 3588 views
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  • Thu, Nov 3 2011 11:25 AM

    • jun1119
    • Not Ranked
    • Joined on Tue, Jan 27 2009
    • Posts 7
    • Points 140
    starting RTL compiler and Encounter Reply

    Hi all

    I am totally new to encounter. I have written a VHDL code and intended to implement it using XFAB xh035 technology. I have read some tutorials online and the manual and found out that to use RC, I have to have a source script (.tcl file) and some library files. Where can I get the .tcl file and library file? I can find some .tcl and .lib files from the XFAB design kit but they do not seem to be appropriate. I have also tried loading my vhdl file without any source script with the command read_hdl -vhdl myvhdl.vhd but nothing happened. When I load it for the second time, I will get this message:

     entity Digital_controller is
    |
    Warning : Replacing existing design unit. [VHDLPT-800]
            : Unit 'default:Digital_controller' in file '/home/chew/rc_digital_ctrl/VHDL/Digital_controller.vhd' on line 11, column 1.
            : A previously analyzed unit is being replaced.
    Warning : Marking out-of-date unit as invalid. [VHDLPT-801]
            : Unit 'default:digital_controller-rtl' depends on overwritten unit 'default:digital_controller'.
            : A unit is considered out-of-date when a unit that it depends on is re-analyzed.
    Warning : Replacing previously read Verilog module or VHDL entity. [HPT-76]
            : Replacing VHDL entity 'Digital_controller' in library 'default' with newly read VHDL entity 'Digital_controller' in the same library in file '/home/chew/rc_digital_ctrl/VHDL/Digital_controller.vhd' on line 11.
            : A newly read VHDL entity replaces any previously read Verilog module or VHDL entity in the same library if its name matches (case-insensitively) the existing module or entity.
        For instance:
            VHDL 'foo'                  replaces  VHDL {'FOO' or 'foo' or 'Foo' or ...} in the same library
            VHDL 'foo' (in any library) replaces  Verilog {'FOO' or 'foo' or 'Foo' or ...} in the same library
     
    A newly read Verilog module replaces any previously read Verilog module if its name matches (case-sensitively) that module.  Further, it replaces any previously read VHDL entity in the same library if its name matches (case -insensitively) that entity.
        For instance:
            Verilog 'foo' replaces    VHDL {'FOO' or 'foo' or 'Foo' or ...} in the same library
            Verilog 'foo' replaces    Verilog 'foo' only
        In addition:
            Verilog 'foo' does not replace Verilog 'FOO' and the two remain as distinct modules.

     How can I start RC? Also, for encounter, are the .lef, tlf, I/O files provided by the foundry as well?

     

    Thank you

    • Post Points: 20
  • Wed, Nov 9 2011 1:22 PM

    • grasshopper
    • Top 25 Contributor
    • Joined on Fri, Jul 18 2008
    • Chelmsford, MA
    • Posts 241
    • Points 3,200
    Re: starting RTL compiler and Encounter Reply
    Hi jun1119, write_template -help would probably provide you a good starting point. I think the message is pretty clear in your previous post. You read twice therefore a number of things are being overwritten. Maybe you though it did not do anything but the messages seem to indicate otherwise. If you read the documentation, you will remember that the design needs to be elaborated after reading so read_hdl -vdhl elab and you should have the design in RC vdir infrastructure good luck, gh-
    • Post Points: 5
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Started by jun1119 at 03 Nov 2011 11:25 AM. Topic has 1 replies.