I have measured loop gain of SRAM during hold operation (during hold it is just two inverters) for different initial conditions on two internal nodes ( Q and Q') and as expected, the two stable solutions will be with loop gain lower than 1.
Loop gain is measured by putting AC source on one of the internal connections and measuring Vout/Vin of this AC source.
DC operating point is secured by putting DC source with large inductance at two internal voltage Q and Q'.
I tried to do the same for write operation which means to add 2 access transistors. I would expect to see only one solution (vdd,0) or (0, vdd) with loop gain