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 RTL_compiler SDF 

Last post Wed, Aug 3 2011 4:30 AM by legolas. 8 replies.
Started by archive 20 Jul 2006 02:29 AM. Topic has 8 replies and 4468 views
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  • Thu, Jul 20 2006 2:29 AM

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    RTL_compiler SDF Reply

    Hi,

    I need to simulate a gate-level netlist from RC 4.2.2
    Can anybody knows how to generate an
    sdf file from RC?

    I've used the "write_sdf" command but the program says
    that it's obsolete and doesn't accept any option.
    Moreover the RC documentation doesn't tell
    anything about "write_sdf"

    Thank you.


    Originally posted in cdnusers.org by giohdl
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  • Thu, Jul 20 2006 7:13 AM

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    RE: RTL_compiler SDF Reply

    Hi giohdl,
    The write_sdf is an unsupported command, but it should work to give you a basic SDF. The syntax is:

    write_sdf > filename

    There's another way to get SDF is to use BuildGates (bgx_shell) from RC package. The basic script is:

    invoke BuildGates: bgx_shell

    read_dotlib your_library
    read_verilog -st your_netlist
    write_sdf file_name


    Originally posted in cdnusers.org by synthman
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  • Thu, Jul 20 2006 12:21 PM

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    RE: RTL_compiler SDF Reply

    Thank you synthman,

    I'll try with BuildGates because
    I need to specify some option
    in the SDF file.


    Originally posted in cdnusers.org by giohdl
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  • Tue, Jul 25 2006 2:45 AM

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    RE: RTL_compiler SDF Reply

    Hi Giohdl,

    Another way is to simulate without sdf (i.e. 0 delay, unit delay etc). Usually, this is enough. What is the use of timing before P&R?

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
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  • Tue, Jul 25 2006 4:51 AM

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    RE: RTL_compiler SDF Reply

    Hi EngHan,

    I think you're right in general.
    My circuit contains several interconnected FSMs so
    I've preferred to simulate before P&R
    avoiding zero delays in cells.

    Regards,
    Giohdl


    Originally posted in cdnusers.org by giohdl
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  • Tue, Jul 25 2006 7:20 AM

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    RE: RTL_compiler SDF Reply

    Unit delay can lead to you spending time debugging issues that don't exist. Avoid like Martha Stewart's stock tips ;-)

    Since you can't really build an SDF that will realistically reflect your final timing atleast until CTS is done, then here are two alternate solutions that I've used but no-one has suggested thus far:

    1) Create and compile a modified version of your verilog/vhdl gate library with 1nS clk->q (or qn etc) on flops (and latches), then use zero delay for combinatorial cells. Design will now function accurately pre-layout.

    2) Alternately why not create a dummy SDF that attaches delay values to specific cell types rather than specific instances? You can do this quite simply. The following example will annotate a 1ns delay to all flops in the design that are of type "floppy"...

    (DELAYFILE
    (SDFVERSION "2.1")
    (DESIGN "dodgy")
    (DATE "17-May-2006")
    (VENDOR "Shoddy Devices Inc")
    (PROGRAM "Manually created. Annotated all DFFs with CP->Q of 1:1:1")
    (VERSION "1")
    (DIVIDER /)
    (VOLTAGE 1.65:1.65:1.65)
    (PROCESS "1.5:1.5:1.5")
    (TEMPERATURE 125:125:125)
    (TIMESCALE 1 ns)
    (CELL
    (CELLTYPE "floppy" )
    (INSTANCE * )
    (DELAY
    (ABSOLUTE
    (IOPATH CP Q (1:1:1) (1:1:1))
    )
    )
    )
    )

    At "Shoddy Devices Inc", we've used both methods successfully. However the second method might be simulator depedent. I'd recommend the first method (unless your vendor doesn't give you simulator library source code).

    HTH

    Crispy Duck


    Originally posted in cdnusers.org by crispy_duck
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  • Tue, Jul 25 2006 7:16 PM

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    RE: RTL_compiler SDF Reply

    Hi Crispy Duck,

    Your reply is enlightening. Actually, I am going along your approach but my reply was short... the effort to get gate level simulate correctly depend on many things, so it is hard to generalise.

    What I did is to change the delay directly in the verilog model (std cell, and sometime even IP like memory), those numerbs in the "specify". This does not require additional file, and the simulation run faster and less memory. The delays are as what you suggest; sometime I use a very small delay for clock buffer, and use the actual delay for delay cell.

    To be more complete, typically we also have to tune the testbench, and sometime adjust the cycle where the data will start to appear. Also have to disable the hold/setup/etc of the synchonisers so that the control-logic does not end up with all "X". Depend on the library and the version of the software you use, you have to patch the SDF to make it "annotatable" (for example you have posedge in .lib, but not in the verilog model). In my last project, I have to use a patched version of Encounter to generate the sdf and 5.* cannot (I might remember wrongly here, but just get the idea) with setuphold / recrem (so that -ve check is supported). Lastly, remember to check the timescale has sufficient accuracy. I think this list can add on; there is always something new in every project.

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
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  • Wed, Jul 26 2006 8:38 AM

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    RE: RTL_compiler SDF Reply

    I think this list can add on; there is always something new in every project
    And we still make all the old mistakes too ;-)


    Originally posted in cdnusers.org by crispy_duck
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  • Wed, Aug 3 2011 4:30 AM

    • legolas
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    Re: RE: RTL_compiler SDF Reply

     Hi EngHan,

    I read your comment saying that you solved some SDF annotation problems using an Encounter patch. Kindly share the solution if the problem was same as below:

     When I try to do an sdf annotation in Cadence I get lots of warnings like:

    ncelab: *W,SDFGENNF: Generic "TPD_ip1_op_posedge" not found in component "test.dff_1.g16:" <./gen_test1.sdf, line 20>.

    The generic "TPD_ip1_op" is present in the library vhdl model file but the _posedge generic is not present.
     

    Also, I use the write_sdf command in Encounter after P&R and CTS to generate the SDF file, is that correct?

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Started by archive at 20 Jul 2006 02:29 AM. Topic has 8 replies.