Hi Crispy Duck,Originally posted in cdnusers.org by EngHan
Your reply is enlightening. Actually, I am going along your approach but my reply was short... the effort to get gate level simulate correctly depend on many things, so it is hard to generalise.
What I did is to change the delay directly in the verilog model (std cell, and sometime even IP like memory), those numerbs in the "specify". This does not require additional file, and the simulation run faster and less memory. The delays are as what you suggest; sometime I use a very small delay for clock buffer, and use the actual delay for delay cell.
To be more complete, typically we also have to tune the testbench, and sometime adjust the cycle where the data will start to appear. Also have to disable the hold/setup/etc of the synchonisers so that the control-logic does not end up with all "X". Depend on the library and the version of the software you use, you have to patch the SDF to make it "annotatable" (for example you have posedge in .lib, but not in the verilog model). In my last project, I have to use a patched version of Encounter to generate the sdf and 5.* cannot (I might remember wrongly here, but just get the idea) with setuphold / recrem (so that -ve check is supported). Lastly, remember to check the timescale has sufficient accuracy. I think this list can add on; there is always something new in every project.