Hi Crispy Duck,Originally posted in cdnusers.org by EngHan
Before the technical discussion, I am surprise that you are in Europe
as "Crispy Duck" sound Asian. A surprise for you too; I am in Paris,
but will be in Asia next month.
You bring up a good point to explain why depending on who you talk to,
some designers want the clock tree to be after the clock gater
(obviously to save power), and some designers want the clock tree to be
before the clock gater (obviously to meet timing).
In the design that I have here, the clock gaters at the base of the
clock tree are hand instantiated, and there is always a pair of FFs
(like the synchroniser) to drive the enable of the clock gaters. In
this way, the logic from the FF to the clock gator is just a wire, and
meeting timing become easy.
It is tricky to decide what should be the latency for the pair of FFs
(in front of the clock gator). Ideally, they should have shorter
latency. However, if you want to include them in the scan chain, then
it is better to balance them. Also depend on where you place the clock
gater. If it is placed next to the PLL, and is miles away from the core
(and somehow you decide to place the pair of FF next to the clock
gaters), then it is better to not balance the latnecy, and also exclude
them from the scan chain (too many if here...).
Now, back to the original question. If the designer does not know the
impact of clock gaters on timing closures, the backend engineer will
suffer; and the quality of the layout will be bad. The new RC 6.1 has
some feature that can merge/split the enable condition of clock gaters.
This might help, or make thing worse. Also, if timing closue due to
clock gater inserted by the tool is a problem, then use a smaller
fan-out for the clock gater (and don't do declone after that. "declone"
is actually merging clock gaters together...). This will move the clock
gater "near" to the FF, and thus have similiar clock latency.
PS: CD, could you send me a mail at email@example.com. Would
like to introduce some of the works I am doing to a experienced backend
engineer like you.