Hi, Originally posted in cdnusers.org by crispy_duck
We don't use custom wireload models. Our synth is run using the smallest "realistic" model in the library (auto selection is disabled), and is purely use to allow us to have some load on nets when running optimisation. Our real aim is to get a netlist into layout as quickly as possible, and utilise post-placement optimisation to achieve better timing results.
The only thing we try to push for in synth is the fastest architecture for things like adders etc. However we do try to ensure that the resultant netlist doesn't utilise many high drive-strength cells (instead reserving them for the layout opt phase).
Whether using custom or library wireloads, you run into issues when timing between blocks or at the toplevel. Yet in placement, the decisions made by the synth tool can be completely wrong.
Of course, someone will now come along and give an alternative view.......