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 Problems in custom design verification using LEC 

Last post Mon, Sep 12 2011 8:21 AM by croy. 3 replies.
Started by sunkimi 06 Sep 2011 09:52 PM. Topic has 3 replies and 3607 views
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  • Tue, Sep 6 2011 9:52 PM

    • sunkimi
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    • shanghai, Shanghai
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    Problems in custom design verification using LEC Reply
    Hi all,

    There is a problem when using LEC10.1 check for custom design (named module A).I checked the Module A two times. First, I check it alone, that is set module A as root module, and then abstract and compare. The result shows that the Golden and Revised design is equivalent.Second, I check it during hierarchical comparison. Problems come here. The constraints are the same as the first comparison. But the result shows the logic between the Golden and Revised is not equivalent.I find that reason may be is that during hierarchical comparison the LEC cannot correctly model the abstracted circuit.

    When run first comparison, LEC can find DLAT as a key point in abstracted circuit, But during the second hierarchical comparison LEC cut the combination feedback as a key point (DLAT has a combination feedback to hold the value). That confused me. How to control LEC to model the circuit.
    The following message showed during the hierarchical comparison. But not appeared during the first comparison.

    // (F3) Cut 21 feedback loop(s), 14 with name

    I have tried some ways to fix the problem. But it cannot works.  

    Any good ideas?

    Thanks.

     
    • Post Points: 20
  • Thu, Sep 8 2011 11:34 AM

    • Sean Lee
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    Re: Problems in custom design verification using LEC Reply

    Hi sunkimi,

    It sounds like abstraction engine results are different on module vs design level abstraction.

    For hierarchical comparison, I would try to abstract module A first, then follow it up by rest of the abstraction. abstract logic -module A abstract logic ..rest of the design.. ..run hier compare.. See if this helps.

    • Post Points: 20
  • Sun, Sep 11 2011 1:21 AM

    • sunkimi
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    • shanghai, Shanghai
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    Re: Problems in custom design verification using LEC Reply

    hi sean,

    Thank you for your reply.
    I have tried the way you proposed. Yes, it can work for module A. But other modules met the problem the same as module A did. That is other module (module B) has a different result from the first comparison.The state element (DLAT/DFF) cannot be abstracted the same one during module and hierarchical comparison.I do not know the reason. It’s a bad thing for me. 

    • Post Points: 20
  • Mon, Sep 12 2011 8:21 AM

    • croy
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    Re: Problems in custom design verification using LEC Reply

    Hi sunkimi

     

    Please create a Service Request at http://support.cadence.com so someone from Customer Support can help you.

     

    Chrystian

     

    • Post Points: 5
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Started by sunkimi at 06 Sep 2011 09:52 PM. Topic has 3 replies.