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 Can't time design correctly with generated clock 

Last post Thu, Feb 10 2005 9:03 AM by archive. 3 replies.
Started by archive 10 Feb 2005 09:03 AM. Topic has 3 replies and 1913 views
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  • Thu, Feb 10 2005 9:03 AM

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    Can't time design correctly with generated clock Reply

    When the source clock for a generated clock is from an internal module, report_timing times launch and capture off of the same edge of this generated clock.

    create_clock -name sclk -period 10 top/U1/U23/port2
    create_generated_clock -name gclk -source sclk -divide_by 8
    ....

    When doing timing report, the launch clock is gclk at time 0 and capture clock is gclk at time 0. So, the path always misses timing.

    Have anybody seen this in their design?


    Originally posted in cdnusers.org by mximdal
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  • Thu, Feb 10 2005 9:13 AM

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    RE: Can't time design correctly with generated clock Reply

    Do you mean report_timing in late mode or early mode? In early mode, launch and capture edge are both at 0.


    Originally posted in cdnusers.org by synthman
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  • Thu, Feb 10 2005 9:19 AM

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    RE: Can't time design correctly with generated clock Reply

    Another thing to check is to use 'report_clocks -generated' to see if the phase shifts for this clock are correct.


    Originally posted in cdnusers.org by synthman
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  • Fri, Feb 11 2005 3:56 PM

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    RE: Can't time design correctly with generated clock Reply

    Synthman,

    Thanks for the reply. Figured out that the clock should be coming from top port. So things are fine now. ;-)


    Originally posted in cdnusers.org by mximdal
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Started by archive at 10 Feb 2005 09:03 AM. Topic has 3 replies.