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 clocks being turned into signals 

Last post Mon, Feb 7 2005 8:55 AM by archive. 1 replies.
Started by archive 07 Feb 2005 08:55 AM. Topic has 1 replies and 1113 views
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  • Mon, Feb 7 2005 8:55 AM

    • archive
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    clocks being turned into signals Reply

    Using 5.13 Buildgates and have run into some issues fixing warnings from check_timing. check_timing reports that clocks are now signals, even though they were properly defined as clocks using the set_clock/set_clock_root routine. When I try to specfically do a set_clock_root for a pin I know is on the clock net using:
    set_clock_root -clock MAIN_CLK U1/data_reg_0/CP
    I get the warning:
    ""U1/data_reg_0/CP is a data pin. Clock assertion ignored. Try removing assertions...""
    In our library for this flip-flop, CP is a clock pin. Is there some assertion that should be applied to our flip-flops in our library?


    Originally posted in cdnusers.org by rs_brandt
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  • Mon, Feb 7 2005 9:16 AM

    • archive
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    RE: clocks being turned into signals Reply

    It sounds like a library related problem. Make sure this pin has the attribute 'clock: true;' in the library. After you read in the library and netlist, and before setting the constraint try:

    get_timing MAIN_CLK U1/data_reg_0/CP clkordatapin

    If it returns 'DATA' not 'CLOCK' then it's most likely something wrong with the library.


    Originally posted in cdnusers.org by synthman
    • Post Points: 0
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Started by archive at 07 Feb 2005 08:55 AM. Topic has 1 replies.