I am developing a new type of multiplier. For that I wrote the VHDL code, and did the synthesis with and without clock contraints. Now I want to compare this architecture with other multiplier architectures. I have got two options;
1. Create the structural VHDL code for other architectures of the multipliers. This will require hand coding and knowledge of all other architectures and will need a lot of time. It will also requite thorough testing to avoid any mistake.
2. Use RTL compiler, and somehow force the tool to synthesize desired architectures and report the area, clock and power. I was wondering
a) if its possible in RTL compiler to select a specific architecture.
b) Is there any documentation available for the kind of architectures used by RTL compiler. I just synthesized a multiplier and it got slow/booth type multiplier. This multiplier has a critical path of almost 3ns at 90nm. I always thought booth multiplier is a serial multiplier, however this one produces a result every cycle.
c) Any input on the comparison methodology that I am following will also be appreciated.