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 Multiplier Selection in RTL compiler 

Last post Mon, Aug 8 2011 3:40 AM by smdunga. 1 replies.
Started by AliShami 26 Jul 2011 06:29 AM. Topic has 1 replies and 4062 views
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  • Tue, Jul 26 2011 6:29 AM

    • AliShami
    • Not Ranked
    • Joined on Tue, Sep 2 2008
    • Posts 3
    • Points 45
    Multiplier Selection in RTL compiler Reply

    Hello Everyone

    I am developing a new type of multiplier. For that I wrote the VHDL code, and did the synthesis with and without clock contraints. Now I want to compare this architecture with other multiplier architectures. I have got two options;

    1. Create the structural VHDL code for other architectures of the multipliers. This will require hand coding and knowledge of all other architectures and will need a lot of time. It will also requite thorough testing to avoid any mistake.

    2. Use RTL compiler, and somehow force the tool to synthesize desired architectures and report the area, clock and power. I was wondering

    a) if its possible in RTL compiler to select a specific architecture. 

    b) Is there any documentation available for the kind of architectures used by RTL compiler. I just synthesized a multiplier and it got slow/booth type multiplier. This multiplier has a critical path of almost 3ns at 90nm. I always thought booth multiplier is a serial multiplier, however this one produces a result every cycle.

    c) Any input on the comparison methodology that I am following will also be appreciated.

    Regards

    Ali

    • Post Points: 20
  • Mon, Aug 8 2011 3:40 AM

    • smdunga
    • Not Ranked
    • Joined on Thu, Jul 14 2011
    • Bangalore, Karnataka
    • Posts 2
    • Points 10
    Re: Multiplier Selection in RTL compiler Reply

    Hi Ali,

    Hope this attribute can be useful for you.

    user_speed_grade

    It can have the following values: {very_slow | slow | medium | fast | very_fast}

    Its a Read-write subdesign attribute. Allows you to choose a fixed implementation of an internal RTL Compiler component, such as a datapath component. A component can have several implementations with different speeds. RTL Compiler automatically determines which implementation to choose to meet timing and area requirements, but this attribute allows you to choose a different implementation.

    Note: If you choose to explicitly control this process through the user_speed_grade attribute, then you must do so after using the synthesize -to_generic command. Otherwise, RTL Compiler will ignore the user specified speed grade and implement an architecture that may or may not coincide with the specified speed grade.

    Rgds Srini

    • Post Points: 5
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Started by AliShami at 26 Jul 2011 06:29 AM. Topic has 1 replies.