My design 'foo' imports a hard macro for a subdesign 'bar', referenced via a bar.lef and bar.lib. One edge of foo abuts with an edge of bar with bar's pins on that edge passed directly to foo's ports. Some of the bar output pins are constants, and thus bar.lib lists a 'function' with a constant value for those pins. RC seems to want to buffer its version of those ports rather than just connect to the output pins of the bar (they are buffered internal to bar, so there is no ESD concern).
The problem is that there is no room to drop a buffer which leads to hilarious results (the buffer is placed many mm away). I'd like to instruct RC (and subsequent velocity runs) to connect those ports directly without any buffering. I [perhaps foolishly] tried:
set_attribute iopt_avoid_tiecell_replacement true [dc::get_ports o_*]
It didn't work (or perhaps I applied this at the wrong point in the flow)--Any suggestions?