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 How to design CHIPEDGE using encounter 

Last post Tue, Feb 11 2014 11:49 PM by stblock. 4 replies.
Started by ada86831 09 Jun 2011 12:00 PM. Topic has 4 replies and 2948 views
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  • Thu, Jun 9 2011 12:00 PM

    • ada86831
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    • Joined on Thu, Jun 9 2011
    • Posts 2
    • Points 40
    How to design CHIPEDGE using encounter Reply

    Hi, All,

    We try to fabricate our chip with MOSIS and  submit our design. But there is an error during DRC ERROR: no CHIPEDGE seen.
    We ask help for MOSIS technical support and they say:

    "CHIPEDGE is something you can teach Encounter to draw for you", it is a special Encounter instruction sequence. You will have to search your Encounter documentation to find it. Search on keywords such as "drawing a bounding box polygon" or "chamfer" or even "CHIPEDGE" might give you a hit. With that sequence you can force Encounter to draw the CHIPEDGE polygon directly".

    We search the whole encounter document but cannot get a hit. If anyone know something like this, please help us.

    We appreaciate 

     

    Thanks

    • Post Points: 20
  • Mon, Jun 27 2011 7:38 AM

    • Kari
    • Top 10 Contributor
    • Joined on Tue, Jul 15 2008
    • Cary, NC
    • Posts 695
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    Re: How to design CHIPEDGE using encounter Reply

     I've always used Virtuoso to design the CHIPEDGE. Usually there is a design kit from the foundry that contains the pieces you need to put it together.

    • Post Points: 20
  • Mon, Feb 10 2014 6:54 PM

    • stblock
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    • Joined on Mon, Jan 20 2014
    • Posts 3
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    Re: How to design CHIPEDGE using encounter Reply

    Hi Kari,

     

    I was wondering if you could provide more details regarding adding the GUARDRING, CHIPEDGE, GUARDEDGE, LOGOBND, etc. I have found some cells in Virtuoso and am also brand new to the tool.  Is it fairly easy to modify the chipedge for my die size? Also, do you have any references or advice?

     Thank you! 

    • Post Points: 20
  • Tue, Feb 11 2014 12:07 PM

    • Kari
    • Top 10 Contributor
    • Joined on Tue, Jul 15 2008
    • Cary, NC
    • Posts 695
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    Re: How to design CHIPEDGE using encounter Reply
    It's been a VERY long time since I've done this, so I won't be able to give you step-by-step instructions, but usually there are corner pieces and edge pieces that contain all the layers you need. If there is only one kind of each, you may need to rotate them for the different corners/sides of your chip. Then, to get the right size, you will need to select just the edges of the shapes on all layers and stretch them to be the length you need. You can probably leave the corner pieces untouched and stretch the edge pieces to meet them. Consult the Virtuoso user guide for how to select just the edge and stretch it. This may or may not be how your design kit works, but hopefully it came with an app note or some other instructions.
    • Post Points: 20
  • Tue, Feb 11 2014 11:49 PM

    • stblock
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    • Joined on Mon, Jan 20 2014
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    Re: How to design CHIPEDGE using encounter Reply

    Thank you Kari,

     

    I'm starting by using the crackstop cell that is included by the foundry, but I'm having all types of issues with it.  Apparently it is a P-cell, (parameterized cell), but I'm not sure how to modify the properties of it for the dimensions of my die.

     My current process is this:

    setup cds.lib and open virtuoso, but then I get an error from virtuoso saying  

    "There is a conflict in techfile graph (cmos32). Look at the techfile reported error message in CIW. Correct techfile conflict before proceeding"   Then in the CIW window I get thjese messages:

    *WARNING* (TECH-2000178): A Purpose Number conflict has been detected in the technology hierarchy. It is caused by the following list of purposes: cmos32/cont0 (#40), cdsDefTechLib/P40 (#40);

    *WARNING* Technology database conflict: There are purpose numbers which conflict in the incremental  techlibs

    *WARNING* (TECH-2000050): Unable to set references on tech because conflicts would results in tech cmos32

     

    So in my cmos32soi library (specified in my cds.lib), there is a tech.db.  Also it appears virtuoso loads the default tech.lib from cdsDefTechLib, but for some reason this is causing a problem that I can't figure out.

     

    If I press okay on the error message window that pops up when virtuoso starts, my procedure is as follows for creating my own crackstop:

    I create a new library (Tools-->Library Manager)

    In the library list I see the following:

    US_8ths, analLib, basic, cdsDefTechLib, cmos32, sample, sbaLib 

     

    I then click on File--> New Library, I specify a directory name called mynewlibrary, attach to an existing technology library, set the technology library as cmos32

     

    Then I click on the cmos32 library, highlight the crackstop cell, and create a copy to my 'mynewlibrary'. When I then try and open up the layout view (which is the only view I have), I am unable to edit any of the parameters, I don't know how. Sometimes I am able to select the crackstop, othertimes not, but I am always able to see it.

     

    I was wondering if you have any advice or anything you notice I am doing wrong?

     

    Thank you very much 

    • Post Points: 5
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Started by ada86831 at 09 Jun 2011 12:00 PM. Topic has 4 replies.