Home > Community > Forums > Cadence Academic Network > Layout of Triple Well NFET without Pcell

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Layout of Triple Well NFET without Pcell 

Last post Fri, Jun 10 2011 8:43 AM by bnugent. 1 replies.
Started by bnugent 09 Jun 2011 11:54 AM. Topic has 1 replies and 632 views
Page 1 of 1 (2 items)
Sort Posts:
  • Thu, Jun 9 2011 11:54 AM

    • bnugent
    • Top 500 Contributor
    • Joined on Thu, Jun 9 2011
    • Cambridge, MA
    • Posts 20
    • Points 280
    Layout of Triple Well NFET without Pcell Reply
    Hello all, I was recently tasked with drawing Pcells of nfetxs layer by layer. I successfully completed a generic nfetx, but am having difficultly with the nfettwx. I have gotten the triple well (nfettwx) to pass DRC with no errors, however, when I run the LVS (Assura) errors pop up. They are: *ERROR* Device 'nfettw(Generic)' on Schematic is unbound to any Layout device. *ERROR* Device 'nfet(Generic)' on Layout is unbound to any Schematic device. I believe the errors indicate that: In layout it recognizes the nfetx lying in the triple well, but does not recognize that it is apart of the whole block, the nfettwx. In the schematic it recognizes that there should be a nfettwx in the layout but does not see it there. My question, has anyone tried drawing an nfettwx layer by layer and run into this problem? I'm relatively new to this version of cadence (IC6.1.4) so any help would be appreciated! Brian N
    • Post Points: 5
  • Fri, Jun 10 2011 8:43 AM

    • bnugent
    • Top 500 Contributor
    • Joined on Thu, Jun 9 2011
    • Cambridge, MA
    • Posts 20
    • Points 280
    Re: Layout of Triple Well NFET without Pcell Reply
    Message Resolved
    • Post Points: 5
Page 1 of 1 (2 items)
Sort Posts:
Started by bnugent at 09 Jun 2011 11:54 AM. Topic has 1 replies.