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 Help for capacitor layout in cadence spectre 

Last post Fri, Jun 3 2011 12:43 PM by SharksFan. 1 replies.
Started by Analog Design 01 Jun 2011 12:07 AM. Topic has 1 replies and 1859 views
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  • Wed, Jun 1 2011 12:07 AM

    Help for capacitor layout in cadence spectre Reply

     Hi,

        In my schematic +ve terminal of capacitor is connected to one terminal and -ve terminal is connected to some fixed DC voltage. I am donig layout in cadence vurtuso version IC514 . It is giving some error like below

     

    The minimum overlap of M1 ground plate to LSM is 10um .

     

    What does it mean ?

    Can I place metal contacts over metal contacts ? 

    • Post Points: 20
  • Fri, Jun 3 2011 12:43 PM

    • SharksFan
    • Top 200 Contributor
    • Joined on Thu, Apr 22 2010
    • Santa Clara, CA
    • Posts 40
    • Points 640
    Re: Help for capacitor layout in cadence spectre Reply

    You are giving an incomplete picture here, so I will state some assumptions about what you are doing/using.

    I assume you are running a design rules check (DRC) which is producing this error message.  You didn't state what process and PDK you are using, nor did you state the type of capacitor.  For some caps like MIMs, there may be rules associated with nearby metals and rules for the metal connections to either plate of the cap.

     You should look at M1 and how it overlaps LSM, which might stand for the lower side metal or bottom plate of a MIM cap. Make sure it overlaps at least 10 um.  Just a guess though, since so few details are provided.

    • Post Points: 5
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Started by Analog Design at 01 Jun 2011 12:07 AM. Topic has 1 replies.