Ali,Originally posted in cdnusers.org by Kari
I'm can't seem to download your log file, but first I assume you ran v2lvs to convert your verilog to spice, right? (Looks like it from the filename.) When you do this, you have to point to a list of the spice files for the std cells in your design (and rams, IOs, any IP, etc.) If this is the step you're missing, let me know and I can give you some more help with the syntax.