Home > Community > Forums > Digital Implementation > First Encounter pin placement/layer

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 First Encounter pin placement/layer 

Last post Mon, Aug 18 2008 6:53 PM by Kari. 9 replies.
Started by archive 18 Jun 2008 09:02 AM. Topic has 9 replies and 9347 views
Page 1 of 1 (10 items)
Sort Posts:
  • Wed, Jun 18 2008 9:02 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    First Encounter pin placement/layer Reply

    Hi there,

    can anyone tell me how to make Encounter place pins on restricted layers, for example on metals 1 & 2 only. Ultimately i'd like my pins placed on a given boundary edge & in a pre-determined order.

    Thanks

    Stu

    p.s I'm actually an alaog layout guy using Encounter (for the first time) to place and route a large digital block in an analog chip. Apologies for the simple Q's, there will be more.


    Originally posted in cdnusers.org by sreilly
    • Post Points: 0
  • Wed, Jun 18 2008 10:08 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: First Encounter pin placement/layer Reply

    Hi Stu,

    Welcome to the forums!

    You may want to use First Encounter's Pin Editor (Edit->Pin Editor) to accomplish this task. It allows you to preassign pins on certain layers, in user-defined order, and on certain sides.

    If you're looking for more of a way to constrain the location of pins which automatic pin placement will honor, there are constructs available for that as well (pin groups, pin guides, pin constraints, etc).

    Maybe you could have a look at the Pin Editor and post back if that was the kind of thing you were looking for and we can go from there.

    Hope this helps,
    Bob


    Originally posted in cdnusers.org by BobD
    • Post Points: 0
  • Thu, Jun 19 2008 4:01 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: First Encounter pin placement/layer Reply

    Hi Bob, thanks for your reply.

    I seem to be getting somewhere and i followed through the manual regards pin editor. I can now sort of re-position and re-order pins. Now i suppose that if you give pins no placement constraints that First Encounter will place each pin in what it deems to be the most sensible position? My next question having done this, can i tell First Encounter that moving pins for easier route access (on a specified grid) is ok as long as it maintains my specified order?

    Again i will continue to go through the manual but any advice i can get is appreciated.

    Thanks

    Stu


    Originally posted in cdnusers.org by sreilly
    • Post Points: 0
  • Thu, Jun 19 2008 8:01 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: First Encounter pin placement/layer Reply

    Yes, without any constraints when placeDesign runs it places the IO pins such that they are as close as possible to the instance(s) each pin is connected to. I like to visually assess this using "selectIOPin *"- if the tool has done a good job, you should see straight flight lines connecting from each IO pin to the nearest instance each is connected to.

    From there, you can constraint pin placement in several ways. There's a pretty good write up on this subject in the SoC-Encounter User's Guide, described in most depth in the Partitioning section under the "Assigning Pins" section. It's worth noting explictly that the constraints available for partition pins also apply to IO pins (the general convention is that the -cell option should be used with the top cell name specified as the cell). If you're you're unsure what the top cell name is you can use "dbGet top.name".

    Dropping down a level in detail to your specific request of "Can FE place IO pins along a given edge, maintaining the order while optimizing the pin location for easier route access?". I've worked through this scenario in the past with mixed results honestly. Perhaps if I describe the mechanisms used to constrain the tool to do what you're asking for you could try it on your design to see if it aligns with your needs?

    createPinGroup myGroup -cell testcase -pin {out1 out2}
    ->order is important here
    ->do not specify -optimizeOrder if you want the order maintained as specified

    createPinGuide -edge 1 -pinGroup myGroup -cell testcase -layer {2 3}
    ->Edges start at "0" with the lower left corner and increases by 1 for each edge clockwise
    ->Visually, in the floorplan view after createPinGuide you should see small white guides around the edges after this step
    ->By default, the system disallows pins on M1. If you require M1 pins, please post back for further guidance.

    From there, you should be able to "placeDesign" and have the tool place the standard cells and IO pins.

    I should mention that I've seen some quality of results issues while attempting to constrain the tool in this specific manner (order maintained while giving the tool flexibility to determine locations). Pin assignment with groups and guides sometimes likes to stack up the pins at the user-defined minimum spacing rather than truly optimizing their locations when the order is required to be maintained.

    Sometimes, it is easier to write a script using "editPin" to place the pins in the order you like with a user-determined gap between each pin. editPin is smart enough to dodge around power preroutes and such so I thought I'd mention that as an alternative.

    Great questions- keep 'em coming!

    Hope this helps,
    Bob


    Originally posted in cdnusers.org by BobD
    • Post Points: 20
  • Mon, Jun 23 2008 6:57 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: First Encounter pin placement/layer Reply

    Hi Bob, agian thanks for your info. I'd just typed a long winded reply and lost connection before i got to post it, very annoying!!!

    Anyway the short reply was that i need to try a few test cases of constraining the pin placement and compare it no constraint placement. My gut feeling is that its more efficient to let the tool place the pins and then i can deal with the connection at the level above, given that its an analog chip and i'll be custom routing at top-level anyway.

    Do you mind another couple of Q's? (should i start another thread for these, i don't want to clog up the forum)

    1) How do you tell FE (First Encounter) that its ok to stack vias and contacts, it appears not to be at present?

    2) Can i get FE to indicate what % of area of my floorplan is being utilised once i've placed my logic? At present i'm setting my floorplan dimensions BEFORE i place the logic. Is this standard practice as this assume i have reasonable feel for the block size before i place any blocks or do any hook-up?

    Cheers

    Stu


    Originally posted in cdnusers.org by sreilly
    • Post Points: 0
  • Mon, Jun 23 2008 7:56 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: First Encounter pin placement/layer Reply

    Hi Stu,

    You're welcome.

    1) For via stacking, the tool should determine this automatically from rules present in the technology LEF. Either your technology LEF is a crude one (and lacks the details to enable the tool to stack vias) or there's something going wrong. It may also depend on whether you're talking about signal routes or power routes in terms of the needed action on your part to encourage stacking. Maybe you could provide some additional detail on your scenario?

    2) For density you probably want to use a command like "queryPlaceDensity" to assess what the standard cell density is after floorplanning the design. This TCL command is equivalent to clicking the circular green icon with a percent sign on the main FE GUI. The difference between queryPlaceDensity and the density # you target when initializing the floorplan size is that nuances like placement blockages, power preroutes that preclude standard cell placement, placement density screens and the like aren't taken into account when determining the initial size of the design as a percentage.

    It's probably best to post new topics individually so that people can see if there's a subject line they're interested in, but no biggie. Either way.

    Thanks,
    Bob


    Originally posted in cdnusers.org by BobD
    • Post Points: 0
  • Mon, Aug 11 2008 9:17 AM

    Re: RE: First Encounter pin placement/layer Reply

    Hi,

    I am working on AMS design and doing digital block P&R separately, i am getting lot of congestion near the pins (working on 3Metal layer design) after the CTS hold opimization (in the placement stage no congestion) and adding lot of buffers to solve hold violation and the design is not routable with nanoroute.then i increased tried but i got same result.

    1. how to dump the pins and re arrange as per my requirements, any scripts (below mail mentioned, pin editor), plz provide the script if available.

    2. why Encounter is adding lot of buffers in the hold opimization (encounter verson 6.2, AMIS lib with 0.35uTech)

    3. After CTS hold optimization, the utlization is around 75%, then also nanoroute is not able route the design?

    before hold optimization i have used the following command for not put many buffers

                                     setOptMode -fixHoldAtSinkOnly

    4. the design is not routable may be one reason lot of congestion in perticular area, why tool is placing the cells apart because there is lot of space is empty (placement satge, utilization is 60%)

    5. how to dump the pins and re arrange as per my requirements, any scripts (below mail mentioned, pin editor), plz provide the script if available.

    Please suggest ASAP.

    Thanks & Regards,

    Kul

    • Post Points: 20
  • Wed, Aug 13 2008 2:06 PM

    • Kari
    • Top 10 Contributor
    • Joined on Tue, Jul 15 2008
    • Cary, NC
    • Posts 693
    • Points 14,275
    Re: RE: First Encounter pin placement/layer Reply

     Hi Kul,

    As for hold opting - if congestion is causing a problem, try using cell padding starting before placement. You can set a cell padding for your flops the size of a buffer that can get added during hold opt. That way there will be a spot by your sinks to add the buffer.  Check out the command specifyCellPad in the docs. Just before you do your hold opt, remove the padding (so the buffers will be allowed to be placed in the spaces) with deleteAllCellPad.

     Also, report your hold timing before you do the hold opt. What kinds of violations do you see? Sometimes clock balancing is an issue. In those cases, adjusting the clocks slightly can fix thousands of holds without any buffers.

     Hope that helps,

    - Kari 

    • Post Points: 20
  • Sat, Aug 16 2008 12:16 PM

    Re: RE: First Encounter pin placement/layer Reply

    Hi Kari,

    Thanks for the reply. In the placement satge there is no congestion byt after CTS, it is showing the congestion. I have specify the cell padding as "1".

    One thing in my library there are lot of buffers they have made as "dont_use"(especially cts footprint buffers) and tool has only 2 differs to make useof these buffers their fanout is "1X", may be this is he cause to add lot buffer?? suggest on this

    Any script is availabe to rearrange the pin location as required by user. (i tried after dumping the "io" file, trying to findout the pin location and rearrange it, but i was not able to understand on what base tool has taken offset value (whn i measured with ruler, value will be different ) and how tool has placed. plz suggest.

    while doing CTS, we sould use Route Clock net option "YES" or not? ( and one more optbuffer and add buffer these option "YES" or not in CTS spec file, i am in confusion, sorry to ask, plz suggest)

    • Post Points: 20
  • Mon, Aug 18 2008 6:53 PM

    • Kari
    • Top 10 Contributor
    • Joined on Tue, Jul 15 2008
    • Cary, NC
    • Posts 693
    • Points 14,275
    Re: RE: First Encounter pin placement/layer Reply

    Hi Kul,

     Using "1" for the specifyCellPad factor is not doing you much good. If you recall from the docs, the factor is multiplied by the metal2 pitch in the LEF file. A standard buffer in your library could be 10 or so metal2 pitches, so you would want to use 10 instead of 1. (Just an example. Pick the buffer you'd like space reserved for, and divide its length by your metal2 pitch. Then use that number.)

    I think you're onto something with the dont_use and fanout. Typically, we will set_dont_use the really low-strength buffers and a couple of really high-strength ones for general optimization. Then for CTS, we specify in the .ctstch file a small list of buffers/inverters to use. As for fanout, I'm not sure if setting a max_fanout in the sdc file will override what's in the .lib; usually the more restrictive option will take precedence, but we need to look that up to be sure. It's unlikely that the fanouts of your buffers really need to be restricted to 1. Can you ask the vendor about that?

    It is recommended to route the clock nets during CTS. The optAddBuffer option is only relevant if you're doing postOpt - please check out the user guide for more about these options.

    For your io file issue, could you explain more or post a picture? What you are trying to do should work, but we need to figure out why the numbers don't match what you expect.

    - Kari 

    • Post Points: 5
Page 1 of 1 (10 items)
Sort Posts:
Started by archive at 18 Jun 2008 09:02 AM. Topic has 9 replies.