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 LVS after place&route may fail due to clock tree buffers 

Last post Mon, Jun 16 2008 5:36 PM by archive. 4 replies.
Started by archive 16 Jun 2008 05:36 PM. Topic has 4 replies and 2548 views
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  • Mon, Jun 16 2008 5:36 PM

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    LVS after place&route may fail due to clock tree buffers Reply

    Hello All

    An LVS after place&route should compare final layout with input verilog code (i mean that verilog code used as input for place&route tool).

    But during place&route, some new buffers may be added  automatically by the tool which were not in the original verilog code.

    My question is how LVS should realize the new buffers?
    when I run LVS by Calibre, it fails with many error messages like this:

    Error: No matching ".SUBCKT" statement for "BFLVTX1" at line 1490 in file "/tmp/lvsRunDir/_decoder36.v.sp"

    BFLVTX1 is a buffer used from std library.

    Can anyone help me please with this issue?

    Thanks,
    Ali Naderi


    Originally posted in cdnusers.org by Naderi
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  • Mon, Jun 16 2008 5:46 PM

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    RE: LVS after place&route may fail due to clock tree buffers Reply

    Hi Ali,

    LVS is not meant to compare the STARTING verilog to the final layout. It is meant to compare the FINAL verilog netlist to the final layout. All the buffers in the final layout will also be in the final netlist.

    - Kari


    Originally posted in cdnusers.org by Kari
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  • Tue, Jun 17 2008 7:01 AM

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    RE: LVS after place&route may fail due to clock tree buffers Reply

    Hi Kari,

    Thanks for you reply.
    Then how do you make sure your final layout is functioning exactly like the original verilog code?
    Full simulation of final netlist (post-layout) may not be possible as digital designs are usually very large in my case 4M gates. Such simulation time is more than few months.
    In analog, we used compare layout with schematic and the schematic may play a roll like starting verilog codes.

    Regards,
    Ali


    Originally posted in cdnusers.org by Naderi
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  • Tue, Jun 17 2008 9:06 AM

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    RE: LVS after place&route may fail due to clock tree buffers Reply

    Ali,

    To compare your starting verilog to your final verilog and make sure the functionality has not changed, you need to run Conformal LEC. You can also compare the starting RTL to the final verilog. LEC does not verify layout, but if you use LEC to make sure the final netlist is functionally equivalent to the starting netlist and then use LVS to make sure the layout matches the final netlist, you should be good.

    - Kari


    Originally posted in cdnusers.org by Kari
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  • Tue, Jun 17 2008 9:31 AM

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    RE: LVS after place&route may fail due to clock tree buffers Reply

    Okay, the LEC is what I need to learn.
    Thanks again,
    Ali


    Originally posted in cdnusers.org by Naderi
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Started by archive at 16 Jun 2008 05:36 PM. Topic has 4 replies.