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 long wire transition time issues 

Last post Wed, Jun 4 2008 2:41 AM by archive. 14 replies.
Started by archive 04 Jun 2008 02:41 AM. Topic has 14 replies and 4912 views
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  • Wed, Jun 4 2008 2:41 AM

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    long wire transition time issues Reply

    In my current design,some wires are quite long,look like over 3000ums,diriven by a buffer,fe does not report the net has transition violation.it should be a problem for the wires are so long.these pins/path are not constrained,could encounter fix this kind thing?if so,what should i do?


    Originally posted in cdnusers.org by yhu
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  • Wed, Jun 4 2008 2:50 AM

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    RE: long wire transition time issues Reply

    set_max_transition in sdc may solve this. If the transition on this net violates the max limit set, Ecounter sees this as violaton and may fix it during DRV Fix
    Not sure :)


    Originally posted in cdnusers.org by Devi
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  • Wed, Jun 4 2008 2:58 AM

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    RE: long wire transition time issues Reply

    i am sure this is well set,and encounter does fix all the violations which are reported.i think take charge of the path constrained,but it should also handle the path which not constrained,especially for the transition time.3000+um should be a problem.or can anyone provide a way to fix these long wires?


    Originally posted in cdnusers.org by yhu
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  • Wed, Jun 4 2008 3:11 AM

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    RE: long wire transition time issues Reply

    You may face such problem if there is no timing path through this net.
    No timing path can come from a false_path, disable_timing_arc or constant propagation from SDC or tie connection coming from the netlist.
    The transition is calculate by the timer, and the consequence is that is there is no path, there is no transition, so no fix on your long wire.
    The trick you can use is to defined a default SDC, where you only put the set_load, set_input_transition ... constrains.
    Load only this new SDC and run optDesign -drv.
    Now the tools should be able to catsh your long net....

    Pat.


    Originally posted in cdnusers.org by bougantp
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  • Thu, Jun 5 2008 8:14 PM

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    RE: long wire transition time issues Reply

    i checked the sdc, there is no set_load/set_input_transition for the input,and the report_timing -through [net_name] reports the input transition is 0.00. I think a 2000um(space 0.2um,width 0.2um) input net should be a transition violation based .13um process.
    by the way,the set_max_transition is 1.4ns.


    Originally posted in cdnusers.org by yhu
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  • Mon, Jun 9 2008 2:06 PM

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    RE: long wire transition time issues Reply

    Make a copy of your constraint file where all the set_case_analysis statements are commented out. Then do a reportTranViolation with that constraint file loaded. You can use report_cell_instance_timing to check a specific pin you are worried about.

    - Kari


    Originally posted in cdnusers.org by Kari
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  • Mon, Jun 9 2008 8:54 PM

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    RE: long wire transition time issues Reply

    You can try with the following variables: which will not consider set_false_path,set_desable_timing,set_case_analysis , exceptions for transition reporting and fixing , It basically propagates transition through constants .

    setvar dbgPropSlewForUnconstrainedPath 1

    Let me know if this could solve your current Issue??

    Cheers.
    -Mohan




    Originally posted in cdnusers.org by mohanch007
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  • Mon, Jun 9 2008 10:52 PM

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    RE: long wire transition time issues Reply

    Kari,

    reportTansViolation could not report transition violation,but report_cell_instance_timing did report transition violations.

    if use timeDesign -postRoute, no tran vio,then use report_cell_instance_timing,no tran vio,neither.
    if only use report_cell_instance_timing,FE could report tran vios ( i mean spefIn ,then report_cell_instance_timing without any timeDesign or reportTransViolation)

    you know,if there are transition violations,report_cell_instance_timing could report it,but timeDesign could not report it,so how could i fix it?


    Originally posted in cdnusers.org by yhu
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  • Mon, Jun 9 2008 11:01 PM

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    RE: long wire transition time issues Reply

    Mohan

    it could report transition violations,for one or two,i could fix it manually,but for hundreds of (not that many),how could i fix it?

    also,if i spefIn,then timeDesign then reportTranViolation,FE could not report the vios.

    so the step worked is spefIn then reportTranViolation


    Originally posted in cdnusers.org by yhu
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  • Tue, Jun 10 2008 8:24 PM

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    RE: long wire transition time issues Reply

    Hi , Thought the Issues was regarding fixing transition on constant nets , But your Issue was some thing different.
    To address your Issue I need to know the back ground of your environment : like
    What you do is : (and let us know the values too) :
    1. you setAnalysis mode , ( was it set to -setup mode ??)
    2. setExtract mode ( was it -signoff??)
    and also do the below at your end and le me know the results .
    Step-1 : spefIn
    Step-2: selectNet < net with 0ver 3000ums >
    Step-3: reportSelect

    make a note of resistance and cap value on it.

    After doing timeDesign select the same net and do the above Step-1&2 ,

    the whole intention is to know if some thing wrong at yhu end. in doing .

    Once you confirm I will let you know the fixing procedure !! , the mail thing is we need to make to understand that there is a transition violation , if its real .

    cheers,
    -Mohan


    Originally posted in cdnusers.org by mohanch007
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  • Wed, Jun 11 2008 3:06 AM

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    RE: long wire transition time issues Reply

    Mohan

    As you said, AnalysisMode is set to -checkType setup,and ExtractRCMode -engine signOff

    spefIn and selectNseet and reportSelect before and after timeDesign,R is the same.

    if i set ExtractRCMode -engine detail,and there is a transition violation.

    One thing i need to clarify is that for the current design,no "set_drive_cell" and "set_input_transition" and any constrains like this for the input pins.so what is the default? you know ,set_input_transition 0.6 is ok, but set 0.8 will cause transition violations.

    my think is for such a long wire,directly from input,there should be a problem,so how could encounter handle it?


    Originally posted in cdnusers.org by yhu
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  • Wed, Jun 11 2008 11:06 AM

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    RE: long wire transition time issues Reply

    Based on your reply to me (Kari), I still think it sounds like a constraint is masking the transition. You didn't say if you tried a constraint file with no set_case_analysis statments.

    - Kari


    Originally posted in cdnusers.org by Kari
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  • Wed, Jun 11 2008 6:17 PM

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    RE: long wire transition time issues Reply

    Kari
    In this design,no case_analysis was set,but no set_drive and set_input_transition was set,will this be a problem?what is the default?


    Originally posted in cdnusers.org by yhu
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  • Fri, Jun 13 2008 12:54 AM

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    RE: long wire transition time issues Reply

    if i remembered correctly, the default is 0.5ns. You can find this out by adding a set_input_transition to all the input pins with some numebr (try 0.5ns & 1.0ns) and then check the timing report (after timeDesign -postRoute)

    li siang


    Originally posted in cdnusers.org by lisiang
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  • Mon, Jun 23 2008 2:21 PM

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    RE: long wire transition time issues Reply

    Check the following line in your .conf file:

    rda_Input(ui_in_tran_delay)

    This may be what is getting used for the default. It's a good idea to set the input trans in your sdc file.

    - Kari


    Originally posted in cdnusers.org by Kari
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Started by archive at 04 Jun 2008 02:41 AM. Topic has 14 replies.