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 how could FE extract coupled C when doing timeDesign? 

Last post Mon, Jun 2 2008 8:47 PM by archive. 3 replies.
Started by archive 02 Jun 2008 08:47 PM. Topic has 3 replies and 1208 views
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  • Mon, Jun 2 2008 8:47 PM

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    how could FE extract coupled C when doing timeDesign? Reply

    Hi,All based a routed design,when i do timeDesign,FE extracts RC,below is a part of the log: Nr. Extracted Resistors : 1721541 Nr. Extracted Ground Cap. : 1821440 Nr. Extracted Coupling Cap. : 0 actually,it's not what I expected,i wanna coupling cap be expected. i try to setExtractRCMode -coupled true,it does not work,and after doing timeDesign,the -coupled is false when getExtractRCMode.. so ,could anyone help,thanks in advance.


    Originally posted in cdnusers.org by yhu
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  • Mon, Jun 2 2008 10:29 PM

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    RE: how could FE extract coupled C when doing timeDesign? Reply

    To extract coupled cap. during time deisgn, You need to enable -si option of timeDesign.


    Originally posted in cdnusers.org by Devi
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  • Mon, Jun 2 2008 10:29 PM

    • archive
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    RE: how could FE extract coupled C when doing timeDesign? Reply

    To extract coupled cap. during time design, You need to enable -si option of timeDesign.


    Originally posted in cdnusers.org by Devi
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  • Wed, Jun 4 2008 2:34 AM

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    RE: how could FE extract coupled C when doing timeDesign? Reply

    Devi,
    Thanks a lot.


    Originally posted in cdnusers.org by yhu
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Started by archive at 02 Jun 2008 08:47 PM. Topic has 3 replies.