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 JK Flip Flop 

Last post Sat, Feb 26 2011 2:50 AM by Anand T. 4 replies.
Started by Anand T 25 Feb 2011 03:30 AM. Topic has 4 replies and 2322 views
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  • Fri, Feb 25 2011 3:30 AM

    • Anand T
    • Not Ranked
    • Joined on Fri, Feb 25 2011
    • Posts 3
    • Points 45
    JK Flip Flop Reply

    Hello Everyone,

     I am new to cadence and hav designed a JK FlipFlop.

    I need to give a clock signal so that the inputs trigger only at the rising edge.

    Now the outputs change for a change in input if the clock signal is high.

    Its acting like an Edge triggered flipflop.

    I want to know how to make the clock edge triggered.

    I am implementing it in cadence virtuoso...Pls do help me out with this.

     

    Thanks in advance.

    • Post Points: 35
  • Fri, Feb 25 2011 9:52 AM

    • skillUser
    • Top 10 Contributor
    • Joined on Fri, Sep 19 2008
    • Austin, TX
    • Posts 2,598
    • Points 16,075
    Re: JK Flip Flop Reply

    Hi Anand,

    I do not think you have given sufficient details for anyone to be able to answer your question. You say you are using Virtuoso, but you do not say which tool or flow you have used: is your JKFF a transistor based schematic design? a layout, a verilog module, Verilog-A (or Verilog-AMS) or something else (e.g. using an external subcircuit/macromodel for a block)?  Which version of the tools are you using? If simulating the design, are you using Spectre, and if so, which version? Or perhaps you are using a digital simulator, e.g. NC-Verilog ?

    An imprecise question will yield an imprecise answer, or no answer at all.  I cannot glean enough information from your question to know how to answer it, sorry.

    Regards,

    Lawrence.

    • Post Points: 20
  • Fri, Feb 25 2011 9:53 AM

    Re: JK Flip Flop Reply

    Presumably you haven't actually designed a JK Flip Flop then. Countless references on google for this, including http://en.wikipedia.org/wiki/JK_flip_flop

    I don't think this is anything to do with implementing the flip flop in Virtuoso - but more about ensuring that your design is correct. And I'm sure this is covered in lots of books (as well as google, as I said).

    Regards,

    Andrew.

    • Post Points: 20
  • Sat, Feb 26 2011 2:41 AM

    • Anand T
    • Not Ranked
    • Joined on Fri, Feb 25 2011
    • Posts 3
    • Points 45
    Re: JK Flip Flop Reply

    Hi skillUser,

    Sorry about that...i am designing it using cmos,n i had designed a JK latch before...i need a edge trigerred JK Flip Flop.

    I need to design a 8-bit synchronous counter using CMOS, so i want to design an edge triggered JK Flip-Flop.

    I got to know that MSJK work as edge triggered Flip-Flop so trying to design it...I have the gate level representation of MSJK n i need the CMOS representation of it...

    • Post Points: 5
  • Sat, Feb 26 2011 2:50 AM

    • Anand T
    • Not Ranked
    • Joined on Fri, Feb 25 2011
    • Posts 3
    • Points 45
    Re: JK Flip Flop Reply

    Hi Andrew,

    Yes i had designed a JK Latch before...i was designing the flip flop using cmos and was a bit confused....

    Now got  a clear picture about it...

    Anyways thank you for the Response.

     

    • Post Points: 5
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Started by Anand T at 25 Feb 2011 03:30 AM. Topic has 4 replies.