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 LEF with VIA definitions in the PORT section of each PIN 

Last post Wed, Apr 9 2008 11:53 AM by archive. 0 replies.
Started by archive 09 Apr 2008 11:53 AM. Topic has 0 replies and 901 views
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  • Wed, Apr 9 2008 11:53 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
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    LEF with VIA definitions in the PORT section of each PIN Reply

    Having VIAS in the PORTS section of the PINS section for each port including the Power/Ground PINS. 
    Are there any advantages to having this information there?  Is it useful for doing EM & IR drop analysis in SOC Encounter on the Power/Ground NETS? Or is it adding no real advantage except creating a blockage? How is
    it dealt with in RC Extraction? 


    Originally posted in cdnusers.org by soba
    • Post Points: 0
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Started by archive at 09 Apr 2008 11:53 AM. Topic has 0 replies.