We are having the same issue that eppramod has brought up with the VDD and VSS netlist. Most PDK's from fabs have digital cell libraries without VDD and VSS (they usually have VDD! and VSS! and SUB!) and we are having to edit these cell libraries to create VDD, VSS and SUB - we need this to use standard digital cells in handdrawn mixed signal schematics anyway. So we are having to copy over the standard cell library and then hand edit the standard cell library to make it free of the global nets (VDD!, VSS! and SUB!). But after this, if we used such a library to import verilog gate level netlists into cadence we dont have connectivity for the VDD, VSS and SUB pins. Can you help with the following
1) A Skill script to change a standard cell library and convert standard cells such that VDD! can be changed to VDD, VSS! -> VSS and SUB! -> SUB.
2) You mentioned a Skill script that can add wires to VDD, VSS and SUB after a verilog file has been imported - can you please provide this? Also does this work heirarchically?
Please help. Thanks.