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 Import Verilog 

Last post Mon, Sep 16 2013 10:20 PM by Quek. 4 replies.
Started by eppramod 06 Jan 2011 08:55 PM. Topic has 4 replies and 2919 views
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  • Thu, Jan 6 2011 8:55 PM

    • eppramod
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    • Joined on Wed, Sep 9 2009
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    Import Verilog Reply
    Hi, Don't know if this query was raised before here. I am new to doing "Import ==> Verilog" in Cadence Virtuoso. I am having a gate level Verilog netlist and was trying to do Import==> Verilog function through Cadence Virtuoso(icfb). I am getting the import to work but unfortunately the reference dfII library which i am using for "component" symbols have VDD and VSS pins in their symbols. After import I am seeing that these ports are unconnected in the schematic view(as there are no VDD/VSS definition in the verilog netlist). Is there a way to have these pins connected after import? Thanks in advance.
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    • Post Points: 20
  • Fri, Jan 7 2011 5:02 PM

    • Quek
    • Top 10 Contributor
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    • Singapore, 00-SG
    • Posts 1,051
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    Re: Import Verilog Reply

    Hi eppramod

    There is currently no easy way to resolve this. We can solve the problem using either of the following methods:
    a. Use a perlscript to add in VDD and VSS connections to the verilog netlist
    b. Use a skillscript to route the VDD and VSS connections after importing the netlist

    You can use the following perlscript. It adds VDD and VSS to the verilog netlist. It is also available in COS solution 11598626.

    Best regards
    Quek


    #!/usr/bin/perl

    # This script adds power pins to a verilog netlist
    # Usage: addpower.pl input.v output.v

    if(@ARGV<2) {
       die("Please enter 2 inputs: E.g. addpower.pl input.v output.v\n")
    } #if

    if(!open(inPort, @ARGV[0])) {
       die("Cannot open file @ARGV[0]\n")
    } #if

    if(!open(outPort, ">@ARGV[1]")) {
       die("Cannot create file @ARGV[1]\n")
    } #if

    $pin1="VDD";
    $pin2="VSS";

    while( chomp($inLine=<inPort>) ) {
       $inLine2 = $inLine;
       $inLine2 =~ s/^ *//;
       @myList=split / /, $inLine2;
       if( @myList[0] =~ /module/ ) {
          $inLine=~s/\(/\($pin1, $pin2, /;
       } #if
       if( @myList[0] =~ /input/ ) {
          $inLine=~s/input/inout $pin1, $pin2;\n  input/;
       } #if
       if( $inLine =~ /.*\(..*\(.*\).*/ ) {
          $inLine=~s/\(/\(.$pin1\($pin1\), .$pin2\($pin2\), /;
       } #if
       print outPort $inLine, "\n";
    } #while

    • Post Points: 35
  • Sat, Jan 8 2011 5:42 AM

    • eppramod
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    Re: Import Verilog Reply
    Hi Quek, Thank you for the response. I will try and let you know. Thanks, Pramod
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    • Post Points: 5
  • Mon, Sep 16 2013 12:05 PM

    • ntrichy
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    • Posts 1
    • Points 20
    Re: Import Verilog Reply

    Hello Quek,

     

    We are having the same issue that eppramod has brought up with the VDD and VSS netlist. Most PDK's from fabs have digital cell libraries without VDD and VSS (they usually have  VDD! and VSS! and SUB!) and we are having to edit these cell libraries to create VDD, VSS and SUB - we need this to use standard digital cells in handdrawn mixed signal schematics anyway. So we are having to copy over the standard cell library and then hand edit the standard cell library to make it free of the global nets (VDD!, VSS! and SUB!). But after this, if we used such a library to import verilog gate level netlists into cadence we dont have connectivity for the VDD, VSS and SUB pins. Can you help with the following

     1) A Skill script to change a standard cell library and convert standard cells such that VDD! can be changed to VDD,  VSS! -> VSS and SUB! -> SUB.

    2) You mentioned a Skill script that can add wires to VDD, VSS and SUB after a verilog file has been imported - can you please provide this? Also does this work heirarchically?

     Please help. Thanks.

    • Post Points: 20
  • Mon, Sep 16 2013 10:20 PM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
    • Posts 1,051
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    Re: Import Verilog Reply

    Hi Ntrichy

    Just a gentle reminder not to append to an old thread. This thread has already ended in Jan 2011. Please always start your question in a new thread.

    1. You can modify the skillscript in COS article 1843566.

    2. I think there is a mis-understanding. I meant that it is possible to code a skillscript to add VDD and VSS wire stubs to the required pins. I don't have such a script.

    Best regards
    Quek

    • Post Points: 5
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Started by eppramod at 06 Jan 2011 08:55 PM. Topic has 4 replies.