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 Warning message in Cadence SiP Layout XL when importing netlist 

Last post Mon, Dec 6 2010 10:33 AM by mikem. 1 replies.
Started by Abel Janeiro 08 Oct 2010 09:54 AM. Topic has 1 replies and 9638 views
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  • Fri, Oct 8 2010 9:54 AM

    Warning message in Cadence SiP Layout XL when importing netlist Reply

    Hi,

    can someone help to solve the problem described bellow?

    This happens when I try to import a netlist using: File --> Import --> logic --> Others

     $PACKAGES
    BGA ! BGA ; BGA
    WARNING(SPMHNI-152): WARNING(SPMHNI-151): Refdes/slot 'BGA/G1' function proper~
    ty 'LOGICAL_PATH @apollo_project_lib.apollo_design(tbl_1):\I18\' deleted.
    WARNING(SPMHNI-152): WARNING(SPMHNI-151): Refdes/slot 'BGA/G1' function proper~
    ty 'SCH_SIZE 1' deleted.
    WARNING(SPMHNI-152): WARNING(SPMHNI-151): Refdes/slot 'BGA/G1' function proper~
    ty 'PRIM_FILE apollo_project_lib.bga' deleted.
    WARNING(SPMHNI-152): WARNING(SPMHNI-151): Refdes/slot 'BGA/G1' function proper~
    ty 'HAS_FIXED_SIZE 1' deleted.
    WARNING(SPMHNI-152): WARNING(SPMHNI-151): Refdes/slot 'BGA/G1' function proper~
    ty 'SWAP_GROUP @apollo_project_lib.apollo_design(tbl_1):\I18\' deleted.
    WARNING(SPMHNI-152): WARNING(SPMHNI-151): Refdes/slot 'BGA/G1' function proper~
    ty 'HARD_LOCATION ' deleted.
    DIE ! DIE ; U1
    WARNING(SPMHNI-152): WARNING(SPMHNI-151): Refdes/slot 'U1/G1' function propert~
    y 'LOGICAL_PATH @apollo_project_lib.apollo_design(tbl_1):\I23\' deleted.
    WARNING(SPMHNI-152): WARNING(SPMHNI-151): Refdes/slot 'U1/G1' function propert~
    y 'SCH_SIZE 1' deleted.
    WARNING(SPMHNI-152): WARNING(SPMHNI-151): Refdes/slot 'U1/G1' function propert~
    y 'PRIM_FILE apollo_project_lib.die' deleted.
    WARNING(SPMHNI-152): WARNING(SPMHNI-151): Refdes/slot 'U1/G1' function propert~
    y 'HAS_FIXED_SIZE 1' deleted.
    WARNING(SPMHNI-152): WARNING(SPMHNI-151): Refdes/slot 'U1/G1' function propert~
    y 'SWAP_GROUP @apollo_project_lib.apollo_design(tbl_1):\I23\' deleted.

    Thanks

    • Post Points: 20
  • Mon, Dec 6 2010 10:33 AM

    • mikem
    • Not Ranked
    • Joined on Mon, Aug 25 2008
    • Posts 7
    • Points 65
    Re: Warning message in Cadence SiP Layout XL when importing netlist Reply

    Just a guess, but it would seem like when the design was originally created, these function properties were assigned to symbols through logic that was imported from Concept HDL, or another schematic capture program. 

    Then, instead of importing logic again by the same method (Concept HDL), you simply imported the logic thru a standard netlist file and it wrote over existing function properties in your SiP design database.

    If the logic you are importing just needs to append to the existing the design, you could de-select the option: "Supercede all logical data" when importing logic.  This will keep existing logic and properties intact.  If your changes are more extensive and your design needs to synchronize with an existing schematic etc., then it may be safer to explore the source of the existing logic and re-import changes thru the original method.

    • Post Points: 5
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Started by Abel Janeiro at 08 Oct 2010 09:54 AM. Topic has 1 replies.