I have come up with a question and i would really want to hear the opinion of more expert people in here about my issue concerning parasitic extraction in an hierarchical design.So,let me pose my question more clearly :
I have an hierarcical design.Let's say that the top level schematic's name is A.
A consists of two sub-cells that i will give them the name B1,B2.
B1 has 6 more sub-cells (C1,C2,C3,C4,C5,C6).
I know hot to perform hierarchical RCX with the Hierarchy Editor tool of Cadence but...if i want to take into account the parasitics of the interconnections of some specific sub-cells what is the way to implement the extraction procedure and take correct results?Can Hierarchy Editor do this or i need another tool of cadence and subsequently an extra license for this?
A testbench for me in the hierarchy editor would be :
C5,C6 --> av_extracted
and i want to extract as well the interconnections between C5-C6 cells and between B1-B2 cells.I should note that all sub-cells have their own physical implementation (layout view in other words).
Thanks in advance for any helpful answer.
My Best Regards,