Hi Suresh,Originally posted in cdnusers.org by Black Lutin
Some additional questions: what is the step ? preCTS, potsCTS, postRoute ?
Generally a big violation as your one is a timing constraint problem. You need to check the clocks (the one on the flop and the one on the out). You can also check the output_delay. Very often a big violation is a "false" violation. You can analyse this violation with the file generated by timeDesign (* _reg2out.tarpt).
Regards ... Luc ...