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 Noise aware PLL design flow 

Last post Thu, Sep 30 2010 10:42 AM by Tawna. 5 replies.
Started by sriram123 28 Sep 2010 12:15 PM. Topic has 5 replies and 2760 views
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  • Tue, Sep 28 2010 12:15 PM

    • sriram123
    • Not Ranked
    • Joined on Thu, Apr 8 2010
    • Posts 8
    • Points 175
    Noise aware PLL design flow Reply
    Hi, I use a collpitts topology for my VCO. While attempting to extract the model of the VCO, I can't give any VSS to my circuit because of this topology. So I get an error when I run PSS/PNOISE. I guess the PLL design flow was designed for LC-VCOs. Is there any work around for the problem? Thanks Sriram
    • Post Points: 20
  • Wed, Sep 29 2010 2:03 AM

    Re: Noise aware PLL design flow Reply

    Sriram,

    What was the precise error? A few pictures might help. I don't thing there's any reason why you can't use a Collpitts oscillator with this flow. You probably need to have the vco_vss source on your testbench, and to create a Vss pin on your "DUT", even if it is not used.

    Regards,

    Andrew.

    • Post Points: 20
  • Wed, Sep 29 2010 6:06 AM

    • sriram123
    • Not Ranked
    • Joined on Thu, Apr 8 2010
    • Posts 8
    • Points 175
    Re: Noise aware PLL design flow Reply
    In the collpitts topology, there is no room for a VCO drive or VSS. So conceptually I can't place VSS probe in the testbench which gives me an error. On the other hand, in LC VCO topology, you need to give a tail current or drive to the VCO due to which you have VSS. Can I just connect the ground node to VSS in this case?
    • Post Points: 20
  • Wed, Sep 29 2010 11:39 AM

    Re: Noise aware PLL design flow Reply

    You can still have it in the testbench but not connected to anything. That's what I was suggesting. You also didn't post the error as I requested. As I said before, pictures would help. 

    Regards,

    Andrew.

    • Post Points: 20
  • Thu, Sep 30 2010 10:00 AM

    • sriram123
    • Not Ranked
    • Joined on Thu, Apr 8 2010
    • Posts 8
    • Points 175
    Re: Noise aware PLL design flow Reply
    Thanks I did as you told and connected VSS to noconnection. The PSS runs for a long time and then returns me this error. I have attached the screenshot. Please help Sriram
    • Post Points: 20
  • Thu, Sep 30 2010 10:42 AM

    • Tawna
    • Top 25 Contributor
    • Joined on Thu, Jul 10 2008
    • Snohomish, WA
    • Posts 208
    • Points 5,500
    Re: Noise aware PLL design flow Reply

     Hir Sriram,

    The error message gave an important clue...you ran out of memory.  Please type in an xterm 

    spectre -h rfmemory 

     like it suggests in the error message.  There are a list of suggestions for you to go through.  If you continue to have difficulty, I suggest contacting Cadence Customer Support.

     

    best regards,

    Tawna

    Best regards, Tawna Wilsey Staff Support AE, Global Customer Support Cadence Design Systems, Inc.
    • Post Points: 5
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Started by sriram123 at 28 Sep 2010 12:15 PM. Topic has 5 replies.