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 Assura LVS error 

Last post Sun, Sep 12 2010 5:22 AM by Quek. 2 replies.
Started by jdgriggs 11 Sep 2010 10:11 PM. Topic has 2 replies and 1537 views
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  • Sat, Sep 11 2010 10:11 PM

    • jdgriggs
    • Top 500 Contributor
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    Assura LVS error Reply
    attached are screen shot of a simple inverter and the layout is drc clean but debug says there is a bad net when the nets match for both...I've done this design 4 times each from scratch and generate the same errors. I have tried using th permute tool but does not seem to help LVS issue. Your assitance is appreciated Regards James
    • Post Points: 5
  • Sat, Sep 11 2010 10:12 PM

    • jdgriggs
    • Top 500 Contributor
    • Joined on Thu, Jul 31 2008
    • Posts 17
    • Points 265
    Re: Assura LVS error Reply
    also attached is the LVS error file....
    • Post Points: 20
  • Sun, Sep 12 2010 5:22 AM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
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    Re: Assura LVS error Reply

    Hi jdgriggs

    Your mos devices have been extracted as generic devices. Hence source and drain pins will not be automatically permuted. VXL layout pin permutation is not related to Assura LVS, hence it will not resolve the problem. You can resolve the problem as follows:

    a. In Assura LVS form, go to "avCompareRules"
    b. Select "Network"
    c. Select "swapPins" and add the following expression for schematic side:
    swapPins("pfet(Generic)" "(p S D)")
    d. Run LVS

    Best regards
    Quek

    • Post Points: 5
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Started by jdgriggs at 11 Sep 2010 10:11 PM. Topic has 2 replies.