The first webinar in the series of webinars organized by Cadence with the System Realization Alliance partners is by XtremeEDA on September 8th at 10AM Pacific time. To register click here.
About the Webinar
Designing integrated circuits from RTL brought about a revolution in semiconductor design about 15 years ago. It was much simpler than assembling transistors by hand. The new methodology made it possible to hire people with less transistor/logic experience and qualifications to do the job of designing semiconductors. It also made it possible to use off-the-shelf IPs to reduce development overall effort. EDA companies provided tools that could read and write standardized languages and formats. All this gave a boost to the number of semiconductors available to system integrators and opened up a portal for creative devices.
However, design sizes have become so large now, that RTL based design approach has become cumbersome and time consuming. The need for increasing processing power and reducing form factor is forcing semiconductor design houses to integrate a lot of IPs in a single device. RTL based approach doesn't yield itself very well to early architectural analysis for such designs. How do you know you are not over-designing or under-designing your chip? Over-designing would mean more than necessary time and resources required to verify and implement the design. Under-designing would mean lost customer! How do you know that an algorithm should be in software or hardware and what would be the impact of such decisions?
Cadence's EDA360 Vision paper discusses the fact that semiconductor design is increasingly a software application driven process. Instead of designing the best possible product that works for everyone, we are increasingly moving to an era where SoCs are being designed to handle particular applications exceptionally well. This will increasingly require a System Realization or Electronic System Level (ESL) platform that allows you to create virtual prototypes of your systems and lets you do hw/sw trade-offs before you commit yourself to the hardware creation writing process, whether using an RTL approach, or more recently emerging high level synthesis.
XtremeEDA is our System Realization Alliance partner with extensive experience in providing ESL model development and verification services. XtremeEDA will be presenting their experiences with ESL in the first of the series of webinars on System Realization. You will get to hear why ESL has only recently begun to take off and how a good ESL methodology can make adoption of ESL techniques easier. By attending the webinar you will be qualified to win a copy of a book on SystemC and TLM Design and Verification that XtremeEDA is giving out.