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 Exporting Verilog netlist from Virtuoso Schematics 

Last post Tue, Aug 31 2010 8:44 AM by Andrew Beckett. 1 replies.
Started by mingfatty 25 Aug 2010 09:11 PM. Topic has 1 replies and 3962 views
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  • Wed, Aug 25 2010 9:11 PM

    • mingfatty
    • Top 500 Contributor
    • Joined on Tue, Mar 16 2010
    • Posts 23
    • Points 385
    Exporting Verilog netlist from Virtuoso Schematics Reply
    Hi Folks, I am using Virtuoso 5.1.41 to perform my simulation (delay, power and etc) and hoping to export the end design in Verilog form so that i ca use encounter to do the place and route for me. I could not find the option in the virtuoso and please kindly help on this issue. Many thanks in advance. Best regards, Ming Fatt
    • Post Points: 20
  • Tue, Aug 31 2010 8:44 AM

    Re: Exporting Verilog netlist from Virtuoso Schematics Reply

    Tools->Verilog Integration->NC Verilog (in the CIW).

    There's a similar menu under Tools from the schematic. 

    Regards,

    Andrew.

    • Post Points: 5
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Started by mingfatty at 25 Aug 2010 09:11 PM. Topic has 1 replies.