Hi KVB,Originally posted in cdnusers.org by Kari
I just posted this to another thread:
As for power stripe widths, these are usually back-of-the-envelope calculations. If you have a wirebond design, you can probably work up a spreadsheet that has the total expected power of the design, the widths and spacings of the stripes, voltage, design size, resistivity of the layers, and calculate a voltage drop. Then keep adjusting the width and spacing numbers until you get an acceptable drop, and start with that. Maybe add a fudge factor somewhere just to err on the conservative side. For flip chips, the calculations are not so easy, but you need much less striping in a flip-chip anyway since power comes down from bumps all over the core. So pick something to start with and do an IR analysis as early as possible.
Hope that helps a bit,