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 Estimating power stripe width 

Last post Fri, Dec 21 2007 1:25 AM by archive. 1 replies.
Started by archive 21 Dec 2007 01:25 AM. Topic has 1 replies and 1135 views
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  • Fri, Dec 21 2007 1:25 AM

    • archive
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    Estimating power stripe width Reply

    Hi All, Can Anyone guide me how to estimate the width of power stripe . Regards, KVB


    Originally posted in cdnusers.org by viswanadhbabu
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  • Thu, Jan 3 2008 1:00 PM

    • archive
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    RE: Estimating power stripe width Reply

    Hi KVB,

    I just posted this to another thread:

    As for power stripe widths, these are usually back-of-the-envelope calculations. If you have a wirebond design, you can probably work up a spreadsheet that has the total expected power of the design, the widths and spacings of the stripes, voltage, design size, resistivity of the layers, and calculate a voltage drop. Then keep adjusting the width and spacing numbers until you get an acceptable drop, and start with that. Maybe add a fudge factor somewhere just to err on the conservative side. For flip chips, the calculations are not so easy, but you need much less striping in a flip-chip anyway since power comes down from bumps all over the core. So pick something to start with and do an IR analysis as early as possible.

    Hope that helps a bit,

    - Kari


    Originally posted in cdnusers.org by Kari
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Started by archive at 21 Dec 2007 01:25 AM. Topic has 1 replies.