Hi Sandeep,Originally posted in cdnusers.org by Kari
Sanjay's advice for die size sounds good to me. Most of the designs I have worked on were I/O-limited, so the die size was already defined by that. But when working on hierarchical blocks, depending on the technology and number of metal layers, we usually try to start the designs around 55 or 60% std cell util. The goal is to not exceed about 75% when the design is complete (clock trees added, design optimized, hold buffers added, etc.) Sometimes you can go higher, depending on pin density, complexity of the design, etc (which all relate to routing congestion). We just start with these numbers, then adjust up or down after some experimenting. This is where the quickness of trialroute and extractRc come in very handy! If something looks promising, we go on to nanoroute and QRC just to be sure things will still look ok.
As for power stripe widths, these are usually back-of-the-envelope calculations. If you have a wirebond design, you can probably work up a spreadsheet that has the total expected power of the design, the widths and spacings of the stripes, voltage, design size, resistivity of the layers, and calculate a voltage drop. Then keep adjusting the width and spacing numbers until you get an acceptable drop, and start with that. Maybe add a fudge factor somewhere just to err on the conservative side. For flip chips, the calculations are not so easy, but you need much less striping in a flip-chip anyway since power comes down from bumps all over the core. So pick something to start with and do an IR analysis as early as possible.
Hope that helps,