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 what is the default input transition for reg clk pin during preCTS stage?  

Last post Wed, Dec 19 2007 2:08 AM by archive. 2 replies.
Started by archive 19 Dec 2007 02:08 AM. Topic has 2 replies and 1268 views
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  • Wed, Dec 19 2007 2:08 AM

    • archive
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    what is the default input transition for reg clk pin during preCTS stage? Reply

    Dear All:

    I want to know what is the default input transition for register clk pin during preCTS stage.
     
    I have read the user guide, got nothing. But from the timing report, I can see different register

    CLK -> Q delay. It is load & clock transition dependent, I can get the load, but how can I get the transition. This is critical for preCTS & postCTS timing correlation. Moreover I don't have set_clock_transition command in my SDC file.

    Or is there a virtual  CTS stage which can make SOC-E know the 'will-be' register clock pin input transition?


    Many thanks


    Originally posted in cdnusers.org by eminemshow
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  • Wed, Dec 19 2007 7:12 AM

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    RE: what is the default input transition for reg clk pin during preCTS stage? Reply

    Is this the variable ui_in_tran_delay in the donfig file that you are looking for?

    http://sourcelink.cadence.com/en/search/DisplayHtmlDoc.jhtml;jsessionidsl=ON3JVX4XPGDLFLA0BEASFEQ?param1=http://sourcelink.cadence.com/docs/db/kdb/2007/June/11341160.html?param2=null?param3=Solutions?param4=11341160?param5=/software/cadence/sldocs/db/kdb/2007/June/11341160.html@en_col?param7=How%20to%20set%20transition/slew%20at%20input%20pins%20of%20clocks%20for%20CTS?


    Sanjay


    Originally posted in cdnusers.org by ssunder@sioptical.com
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  • Wed, Dec 19 2007 9:12 PM

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    RE: what is the default input transition for reg clk pin during preCTS stage? Reply

    Sanjay:

    Many thanks! Sanjay, what you said is right!

    Best Regard

    My msn is eminem198123@hotmail.com

    Hope we can be friends.


    Originally posted in cdnusers.org by eminemshow
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Started by archive at 19 Dec 2007 02:08 AM. Topic has 2 replies.