Dear All:Originally posted in cdnusers.org by eminemshow
I want to know what is the default input transition for register clk pin during preCTS stage.
I have read the user guide, got nothing. But from the timing report, I can see different register
CLK -> Q delay. It is load & clock transition dependent, I can get the load, but how can I get the transition. This is critical for preCTS & postCTS timing correlation. Moreover I don't have set_clock_transition command in my SDC file.
Or is there a virtual CTS stage which can make SOC-E know the 'will-be' register clock pin input transition?