good qn. I know there is some formula out there bu this is what i do. Originally posted in cdnusers.org by pjayasekharan
1. look at a previous design which is similar in size and same process if available.
2. once you have a basic power structure built, you can run FE's statistical floorplan mode power estimation/ir drop estimator. you have to know the pad locations
of the pg pins, and the clock toggle factor/freq . (look at the doc for help).
3. if you dont meet ir drop spec at this stage or you barely meet it, you should provide more stripes or increase ring width etc. i generally try to meet half
of the ir spec limit in floorplan stage.
power dissipation is design related. all we can do is ensure all cells get a voltage close to the supply voltage. we cannot reduce power diissipation.
you also need to feed in a realistic expected power no for step 2 to be accurate.