When you said that your design is about 20 millions gates, In fact it is more intersting to give the number of instances, Which is exactly what the placer has to deal with.Originally posted in cdnusers.org by bougantp
On my side I play with chip which have 3.5 millions instances, Timing driven placement is about 7hours. I aggree it is long but not killer.
At early stage, I deal with what Cadence call Black Blob.
For submodule inside each partition, I replace the full gate level netlist by a dummy one (The blob netlist). Unstead of standard cells, the blobs contains kind of super cells, which is bigger than the standard cells. You can attach hard macro to your blob.
With such tricks my placement tooks less than 2hours, which is definitely better and allow me to make several iteration per day...
Once It seems OK I switch back to the full gates placement.
Be carrefull the Blob definition need a GXL license.