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 how to avoid this problem? 

Last post Sun, Sep 23 2007 12:28 AM by archive. 3 replies.
Started by archive 23 Sep 2007 12:28 AM. Topic has 3 replies and 1847 views
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  • Sun, Sep 23 2007 12:28 AM

    • archive
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    how to avoid this problem? Reply

       I found some paths easy violation as shown in attechment after CTS. The ICG cell is traced through and the skew is balanced between A and C. But the violation easy occur between A and B(ICG cell). How do I avoid this problem?


    Originally posted in cdnusers.org by Dota
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  • Mon, Sep 24 2007 12:22 AM

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    RE: how to avoid this problem? Reply

    A good practice for such ICG cell is to avoid logic from the flop A (Register out).
    Anyway, an alternative to ameliorate timing is to play with ckClone which should push the IGC cell more deeper in the clock tree.

    In pre-CTS mode, if you do have specific trick on your SDC, the TA estimate register A, B and C to be balance.
    By construction we know that register B will be in advance compare to A and C.
    To modelize that, you can add in your SDC
    [i]set_clock_gating_check 1.0 [get_pins {B/E}][/i]
    It will modelize the fact that the clock tree between B and C will take 1.0 ns.
    It will force the pre-CTS optimisation to work more on that path, and to be more in line with your post-CTS db.

    Pat.


    Originally posted in cdnusers.org by bougantp
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  • Mon, Sep 24 2007 2:53 AM

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    RE: how to avoid this problem? Reply

    thanks for your answer, but there are some problem in it.
    set_clock_gating_check is used for path timing check. The tool don't care about timing check in CTS ,so this command seems useless. I think some methods below maybe helpful.
    1. let the CTS not to balance A and C to reduce clock skew between them.
    2. set max delay between A and B to help tool optimize placement.
    any suggestion is welcome.


    Originally posted in cdnusers.org by Dota
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  • Mon, Sep 24 2007 3:06 AM

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    RE: how to avoid this problem? Reply

    set_clock_gating_check is here just to avoid pre-CTS optimization to be to optimistic.
    In standard flow it must be use from synthesis to CTS step.

    I aggree that CTS are no timing aware (it's a shame....), but if you can help the tool a little bit, it will give better result.
    If your Enable path is too long, for sure it will be very difficult to close timing. The only solution might be to play with usefull skew...

    Pat.


    Originally posted in cdnusers.org by bougantp
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Started by archive at 23 Sep 2007 12:28 AM. Topic has 3 replies.