right now, I am working on a project using SoCE4.2. The library I am using contains these kinds of clock buffers, which are all output complementary, Q and -Q. Unfortunately, while I specified them in my *.ctstch file and ran the CTS, the errors appeared:
ckSynthesis Option : -rguide digital_cts/digital_cts.guide -report digital_cts/digital_cts.ctsrpt
**WARN: cell CK01D1 has more than one timing arc. Check the timing libraries.
Buffer CK01D1 specified in the clock tree specification file is invalid.
Usage: ckSynthesis [-clk ] [-report ]
[-rguide ] [-macromodel
] [-check] [-forceReconvergent]
| -ignoreLoopDetect] [-addOriginalNet]
**ERROR: ERROR: Incorrect usage for command "ckSynthesis".
So I have to use those simple normal buffers & inverter instead. Although this time the CTS succeed, I am not quite satisfied with the CTS result report, cause the discrepancy between the rising skew and falling skew is huge:
Rise Skew : 506.3(ps)
Fall Skew : 1358.5(ps)
I guess this is due to the performance of the simple buffer & inverter is not as good as the clock buffer.So I wanna try to use the clock buffer back in the CTS. Can anybody tell me how to fix this cell-CK01D1-has-more-than-one-timing arc problem?
Thanks in Advance!Originally posted in cdnusers.org by Gordonlyn