I have two clock in my design, clk1 and clk2 (generated from clk1 with half frequency with a flop). I also output clk2 for input data synchronization (data can only be input when clk2 is high). Here are my questionsOriginally posted in cdnusers.org by jerry2008
(1) how to align the edges of clk1 and clk2 at the ports (as in the case of behavioral simulation)?
(2) how to sync the input data with clk2 as in behavioral level? since primary input clk is buffered a lot before it reaches the register that latches the data, which in turn is buffered from the primary input port too, is it possible to specify that they arrive at the reg at the same time?
(3) should I set false path between regs in these two clks?
(4) do I need to specify set_clock_latency -source for clk2? if so, it is just the delay of the flop?
(5) a more general question is should I use the same sdc for clk1 and clk2 for prects and postcts?
Thanks in advance!