I had a bunch of transistor devices in schematic, but combined them as one transistor cell in layout (with multiple fingers).
I realized this is probably the toughest way to go.
Instead, I generated a transistor cell in layout for each transistor in schematic, and then overlapped the source or drains
of each transistor layout cell with another to create the interdigitation I desired. This fixed the problem I had, and the cells were
already mapped between schematic and layout.
I guess this is why cadence will not let me map one layout device to multiple schematic devices, since no one would do something dumb like I did. Thank you very much for helping me along the way.