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Extraction of parasitic parameters of a MOS transistor used like switch

Last post Thu, Apr 24 2014 9:36 AM by smlogan. 3 replies.
 Started by Ueue 09 Feb 2010 02:18 PM. Topic has 3 replies and 1596 views
• Tue, Feb 9 2010 2:18 PM

• Ueue
• Joined on Wed, Mar 4 2009
• Pisa, Pisa
• Posts 41
• Points 700
Extraction of parasitic parameters of a MOS transistor used like switch
 Dear all,I need to have a precise estimation of the parasitic capacitances of my MOSFETs, used as switches. I was thinking, for the measure of capacitances to impose a voltage source with voltage Vs increasing linearly with time and measuring the current (proportional to the capacitances). So Vs=K*t. For example connecting the generator to the gate, and the other terminals to ground, I could measure the Cgd and Cgs. Is it a good method?Thanks a lot,Stefano
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• Post Points: 20
• Thu, Apr 24 2014 1:44 AM

• IanX
• Joined on Wed, Apr 9 2014
• Posts 8
• Points 130
Re: Extraction of parasitic parameters of a MOS transistor used like switch
 I have the same problems. I want to design a buffer chain. According to the design procedures from the book by Baker, I need to know the input capacitance of the inverter and the output capacitance of the inverter. What I try to do is do the DC analysis in cadence, then print the dc operating opoint. After that, we can see a lot of parameter listed in the table. However, I felt a little confused. If the input capacitance of the cmos inverter is considered, cin equal to cgs,nmos+ cgd,nmos+ cgs,pmos,+cgd,pmos and cout= cdb,nmos+csb,nmos+cdb,pmos+csb,pmos + the input capacitace of next stage of inverter link.Is that right?From the results of the simulator, cgs is not equal to csg. Both of this two values is negative. Should I just ignore the negative sign and which value I should choose?Thanks!
• Post Points: 35
• Thu, Apr 24 2014 3:03 AM

• Pyroblast
• Joined on Thu, Sep 12 2013
• Posts 27
• Points 435
Re: Extraction of parasitic parameters of a MOS transistor used like switch
 Hi there,I have the same problem. I have search all over the web, thesis, forum, etc and I just can't reach a conclusion. I read that one coud use the print OP and use those values, I read that one should use transient/AC analysis to get a more accurate value however this was contested by some user in the forum that I read that, and so on.The feeling that I have is that:1st. People doesn't want to share how this is done;2nd. No one knows and they are just commenting in forums;I need to design a chain of inverters (drivers) to drive my power devices and I don't have any starting point.Regarding the negative capacitances, that is related to the way the spectre/bsim model does the math. My problem is to know if we can ignore that "minus" sign in order to use the capacitance that we get from print OP (if this is the way to get the capacitances).Taking the advantage of this post, I'd like to know if someone can tell me:1st. How can I get the Kn,p value? (I know that Kn,p = un,p Cox and for that;2nd. How can I estimate the Cox? From the technological documentation I have access to the extracted Tox from the foundr. I can use this value and the respective known equatio to get the Cox? This leads to;3rd. If I can do that, then I can estimate the capacitances using the Cox and the basic equations do compute the Cgs, Cgd, Cgb etc? Regards.Hope get some answers here....
• Post Points: 5
• Thu, Apr 24 2014 9:36 AM

• smlogan
• Joined on Tue, Jun 10 2014
• Posts 105
• Points 1,800
Re: Extraction of parasitic parameters of a MOS transistor used like switch
 Dear IanX,I would approach your issue slightly differently. If you need to determine the input and output capacitances of an inverter, I would simulate the input and output capacitances directly as a function of inverter DC operating point and at a particular frequency. I have a test bench that I use quite frequently to determine the input impedance our output impedances of either devices or larger blocks (switches, buffers, etc.). The test bench applies an AC current to the device under test. A DC voltage is impressed to the device under test using a large inductor. The voltage across and current to the device are measured in an AC analysis, and at a particular frequency, the input reactance is computed to determine the input capacitance.  This method avoids the complexities of using BSIM model paramters to determine input and output capacitances of blocks. It also highlights the very significant impact of such things as Miller capacitance, parasitic routing capacitances (if used with the extracted view of a block). I hope this is useful to you. Shawn  test_cap.png
• Post Points: 5