Delete all buffers between IO ang register 

hi

i need to delete all series of buffers with fanput 1 from input to register & register to output

one way is using deletebuffertree command with selected nets(nets b/w buffers).

can any one tell me how i can get all net names between input & register, register & output using encounter db commands.

regards,

suresh pachha  

Interesting challenge- thanks for posting it.

The first thing I'd mention is that deleteBufferTree -selNet isn't precisely limited to the list of nets it is supplied with.  For example, in this netlist, there are 2 buffers in series before the register:

module testcase(in1, in2);
 input in1, in2;
 wire net1;
 BUFX1 i0(.A(in1), .Y(net1));
 BUFX1 i1(.A(net1), .Y(net2));
 DFFX1 i2(.D(net2));
endmodule 

If you called deleteBufferTree -selNet and supplied it with only "in1" as the net, both buffers would be deleted because deleteBufferTree traverses and tries to delete all the buffers (and inverter pairs) in the tree of the net name you supply.

Because of this, the requirement about limiting the removal to only the buffers with a fanout of 1 is a little trickier than it might otherwise appear.  You might get a good ways towards where you're trying to get if you call deleteBufferTree -selNet with a file containing all the nets connected to IOs.  You could capture that list of nets like this:

set outfile [open sel.net "w"]
foreach net [dbGet -u top.terms.net.name] {
  puts $outfile "$net"
}
close $outfile

Then you could call deleteBufferTree -selNet sel.net and it would delete all of the buffer trees that are connected to IOs.

If you truly needed to restrict this to  nets with a fanout of 1 you'd need to do something more sophisticated where you examine the fanout tree prior to including the IO net to make sure the fanout of each net downstream from the IO net is a buffer or inverter pair and has a fanout of 1.

Let me know what you think of this so far and we can continue our discussion.

Hope this helps,
Bob

Thanks for u r reply Bob.

I already checked about fanout by report_timing on those paths. All buffers or inverters between IOs to register r having fanout 1. 

Actually some IO ports are far away from registers and have direct connections to register D pin(incase of Input port) or Q pin(incase of Output port). I want to delete all the buffers added by optDesign and freshly start building CTS by specifying Input port as root pin and register D pin as leaf pin incase of In2reg path. I tried 2 ways to delete these buffers

1.deletebuffertree with selectnet option and given all the nets b/w input & register

2.deleteclocktree -clk <rootpin> after specifying clock spec.

after deleting buffers i tried cts, it worked but due to this others paths got effected.

can u please tell me at what satge i do cts or buffertreesynthesis and what settings i need to do so that other paths should not be effected. 

Regards,

suresh pachha

I think using a CTS-like approach to build buffer trees for datapaths should only be used when you require balanced latency.  I doubt you need that, so I wouldn't pursue the ckSynthesis nor bufferTreeSynthesis.

What is the design challenge you're trying to overcome?  Is it poor in2reg timing?  If so, I'd try to get the tool to place the registers closer to IO pins in the first place.  A couple of techniques you could try for this:

1. Specify the flops as jtag instances and run the jtag placement prior to placeDesign.
2. There's a utility in the gifts directory (<install_path>/share/fe/gift/scripts/tcl/userAddMenuPullInstsToIos.tcl) that traces and preplaces instances "n" levels from the IO pin close to the IO pin. 

If the concern is something other than in2reg timing, let us know and we can suggest a different approach.  optDesign should be doing a fine job buffering these paths- could you describe a little more about what it's doing poorly?

It's possible that in2reg timing is mis-constrained.  It's pretty common to see IO constraints that are unachievable due to including source latency or not -or- there being difficulty generating timing budgets in general.

Hope this helps,
Bob

The Block floorplan frame after partition from top level has a very narrow area and the pins are palced on that area i can not allow register to place near the IO as it worsen  the reg to reg timing. The IO are nearly 4 to 2 mm away from corresponding registers, I can allow upto 1.5ns dealy for this distance. OptDesign is not working for me. so I decided to do buffertreesynthesis it is working fine. but I am not able to decide at what stage(after palce or after prects opt.) i should apply this method.

 Regards,

suresh pachha