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 size limitation 

Last post Fri, Feb 19 2010 6:55 PM by Andrew Beckett. 1 replies.
Started by zhila 30 Jan 2010 11:29 AM. Topic has 1 replies.
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  • Sat, Jan 30 2010 11:29 AM

    • zhila
    • Not Ranked
    • Joined on Sat, Jan 30 2010
    • Posts 1
    • Points 20
    size limitation Reply
    dear all, i need the constraints limit on size of pmos and nmos transitor in 65nm of tech. i don't have access to cadence tech file information, could any help me, in fact i need lmin, lmax, wmin, wmax in 65nm so gratefull
    • Post Points: 20

  • Fri, Feb 19 2010 6:55 PM

    • Andrew Beckett
    • Top 10 Contributor
    • Joined on Fri, Jul 18 2008
    • Bracknell, Berkshire
    • Posts 869
    • Points 14,105
    Re: size limitation Reply

    Nobody can answer your question without knowing which specific 65nm technology you're using, and even then it's probably not a good question for a general forum such as this. It's almost certainly covered in documentation along with the Foundry's Design Kit.

    Regards,

    Andrew.

    • Post Points: 5
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Started by zhila at 30 Jan 2010 11:29 AM. Topic has 1 replies.