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 ultrasim partitioning error, can I decalre bias node as voltage regulator output? 

Last post Tue, Jan 26 2010 2:43 PM by Andre Baguenie. 2 replies.
Started by huber 18 Dec 2009 01:31 PM. Topic has 2 replies and 1396 views
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  • Fri, Dec 18 2009 1:31 PM

    • huber
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    • Joined on Fri, Dec 18 2009
    • Posts 3
    • Points 45
    ultrasim partitioning error, can I decalre bias node as voltage regulator output? Reply

    I'm trying to simulate a large mixed-signal post-layout extracted (i.e. flat) netlist in ultrasim for functional/timing verification.  Before, when I was running the simulation from a schematic netlist, these ultrasim accuracy settings were sufficient:

    usim_opt sim_mode=ms speed=5

    But now these setting give very strange behavior due to a partitioning problem.  The bias node of my CML logic circuits wanders all over the place, and so does the CML amplitude.  You can see this in the plot.

    CML bias drift

    I believe this is due to different partitions coupling to this node.  Increasing the simulator accuracy gets rid of the artifact, but can have a huge impact on simulation speed.  These are the options I have identified so far that get rid of the bias drift:

    1)  Set global analog=3 or analog=4 to force more conservative partitioning. Increases simulation time by ~10X, which is too much.

    2) Parse the netlist, identify all components that touch the CML bias node, and set sim_mode=a for these components only.  This forces everything that touches the bias node to be in the analog partition.  Transient simulation time is only slightly longer than with default settings above.  But initialization time increases by ~8 hours processing the ~6000 different usim_opt statements.  The log file says "SFE Parser" durring this time.

    3) Declare the bias node as a voltage regulator output with a usim_vr statement.  Simulation time is as fast as option 2 without the long initialization.

    Has anyone used a usim_vr statement like this before?  Do you know what it does?   Is it a Bad Idea to use it like this?

     -Dan

    • Post Points: 20
  • Tue, Jan 26 2010 1:42 PM

    • martinmmuc
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    • Joined on Thu, Jan 15 2009
    • Posts 2
    • Points 40
    Re: ultrasim partitioning error, can I decalre bias node as voltage regulator output? Reply

    I have  similar problems.

     

    The  usim_vr  command/statement  is  a piece  of  ***.

    Partitioning is completely  illogical.

     

    .usim_opt elemcut_file=1  nodecut_file = 1
    *ultrasim: .usim_report partition type=size

    • Post Points: 20
  • Tue, Jan 26 2010 2:43 PM

    • Andre Baguenie
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    • Joined on Mon, Oct 20 2008
    • Velizy, Yvelines
    • Posts 1
    • Points 5
    Re: ultrasim partitioning error, can I decalre bias node as voltage regulator output? Reply
    Hi Martin,

    usim_vr  command is power full command for getting  more aggressive partitioning in case of the virtual supply node, not connected to a voltage source (vsource). You should use it only when this node is a  virtual power net for many digital blocs. It means you have many channel connected active devices connected to this virtual power net.

    For setting correctly usim_vr command, you can define for example the voltage regulator instance and one or multiple virtual supply nets.

    Example:

    .usim_vr subckt=vreg node=[virtual_vddi]

    .usim_vr inst=[X0] node=[ virtual_VDD18]
    Best regards, Andre
    • Post Points: 5
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Started by huber at 18 Dec 2009 01:31 PM. Topic has 2 replies.