I've got the same problem with DRC errors... (It's good to know that I'm a new user of Cadence Allegro)
So, first, I created the symbol of my PCB with route & package keepout (package keepout has constraint with package_height_max because of my PCB will be implement in an aluminium box). After setting those parameters, I create the board project including the drawing of my PCB (*.dra).
Then I import the logic netlist (exported with Allegro Design Entry CIS) and when I place every connectors and components, a DRC error is appearing...
You might found a screenshot of one of this problem.
I'm using Cadence Allegro 16.3 on ASUS X53 Series Windows 7
I hope someone can help me to fix it up... Feel free to ask me some questions if I'm not clear with these explanations.