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 design.io assignment file generation. 

Last post Tue, May 22 2007 4:36 AM by archive. 3 replies.
Started by archive 22 May 2007 04:36 AM. Topic has 3 replies and 1674 views
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  • Tue, May 22 2007 4:36 AM

    • archive
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    design.io assignment file generation. Reply

    Hi all, I am using cadence "Soc Encounter 5.2" in which i imported "design.v" & "design.sdc" from RTL compiler 5.2. How and from where to get "design.io" file to import in "IO Assignment" file option in the basic form of "design import". thanks!


    Originally posted in cdnusers.org by vlsi_dude
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  • Tue, May 22 2007 7:02 AM

    • archive
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    RE: design.io assignment file generation. Reply

    Hi vlsi_dude,

    The IO Assignment file is an optional input. It can be used to instruct the tool where to place IO pins (in a block level design) or IO cells (in a chip-level design). If you want the tool to determine these locations automatically, you can leave this field blank.

    More typically, the locations of IO pins or IO cells are brought in after the Design Import step via a DEF file or a First Encounter ".fp" file. These floorplan files can also define things like the design size, the power grid, and FIXED hard macro locations. If you don't have a DEF or a .fp file, the tool will automatically determine a design size depending on the area of the instances in your Verilog netlist, and when you run "placeDesign" your IO pin locations will be automatically determined.

    If you're working on a block within a hierarchical design, First Encounter can generate the DEF or .fp file. The right thing to do depends what stage in the design process you're in (early on making estimates vs. late in the process and requiring detailed implementation) and whether your metodology is more tops-down or bottoms-up.

    Hope this helps,
    Bob


    Originally posted in cdnusers.org by BobD
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  • Tue, May 22 2007 10:02 AM

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    RE: design.io assignment file generation. Reply

    to add to Bob's comment. You can write out a sample copy of the design.io after you have "create a floorplan" (you need to fill in the blk size or util., aspect ratio...).


    Originally posted in cdnusers.org by lisiang
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  • Thu, May 24 2007 12:01 AM

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    RE: design.io assignment file generation. Reply

    Hi BobD!, I'm working with chip level design which have only pink colured blocks.I'm in the early in the process i.e just after design import. Methodology followed is tops-down. Thanks!


    Originally posted in cdnusers.org by vlsi_dude
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Started by archive at 22 May 2007 04:36 AM. Topic has 3 replies.