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 hexadecimal numbers in veriloga 

Last post Tue, Sep 1 2009 1:38 AM by Andrew Beckett. 3 replies.
Started by Nikolaj 01 Sep 2009 01:11 AM. Topic has 3 replies and 1576 views
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  • Tue, Sep 1 2009 1:11 AM

    • Nikolaj
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    • Joined on Thu, Apr 23 2009
    • Posts 2
    • Points 25
    hexadecimal numbers in veriloga Reply

    Hi,

    I just started using veriloga and have a simple question. Is it possible to assign hex numbers to integers in veriloga ( like you do in C with "int a = 0x0123") ? Couldn't find this anywhere in the veriloga documentation..

    -Nikolaj

    • Post Points: 20
  • Tue, Sep 1 2009 1:29 AM

    Re: hexadecimal numbers in veriloga Answer Reply

    In spectre this isn't supported (you can't use even binary constants such as 1'b1 either).

    In AMS Designer however, this is support by virtue of it being supported in Verilog. The syntax is something like 'h0123 or 16'h0123 (the first is "unsized" and the second form is 16 bits wide).

    Regards,

    Andrew.

    • Post Points: 20
  • Tue, Sep 1 2009 1:36 AM

    • Nikolaj
    • Not Ranked
    • Joined on Thu, Apr 23 2009
    • Posts 2
    • Points 25
    Re: hexadecimal numbers in veriloga Reply

     Ok, thanks for the answer!

    • Post Points: 5
  • Tue, Sep 1 2009 1:38 AM

    Re: hexadecimal numbers in veriloga Reply

    I meant to say that in AMS Designer it is supported for VerilogAMS views - so it's supported in VerilogAMS, not VerilogA. I checked in the VerilogAMS LRM and it's unclear whether such syntax is supposed to be supported in the Analog subset of VerilogAMS.

    Regards,

    Andrew.

    • Post Points: 5
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Started by Nikolaj at 01 Sep 2009 01:11 AM. Topic has 3 replies.