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 effective width less than zero? 

Last post Fri, Aug 7 2009 5:51 PM by modeling. 1 replies.
Started by whlinfei 03 Aug 2009 07:16 AM. Topic has 1 replies and 827 views
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  • Mon, Aug 3 2009 7:16 AM

    • whlinfei
    • Top 500 Contributor
    • Joined on Sun, Mar 15 2009
    • Posts 24
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    effective width less than zero? Reply

    Hi All,

     i am using cadence virtuoso to simulate some cmos circuit, in which there is inverters chain with tapering ratio of T. But When I increase the w/L ratio to a certain level, the simulation error incurred, saying the effective width is less than zero. 

    I am using IBM 30nm process and I couldn't found any model relating to modulation of the width.

    Can anyone help me on it ?

    Many Thanks.

    Best Regards,

    Whlinfei         

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  • Fri, Aug 7 2009 5:51 PM

    • modeling
    • Not Ranked
    • Joined on Fri, Aug 7 2009
    • Posts 1
    • Points 5
    Re: effective width less than zero? Reply

    Check the lmin and wmin set inside the model. Probably one of them is blowing up as you are tapering your W/L values.

    • Post Points: 5
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Started by whlinfei at 03 Aug 2009 07:16 AM. Topic has 1 replies.